参数资料
| 型号： | XCV405E-7BG560I |
| 厂商： | Xilinx Inc |
| 文件页数： | 38/118页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V 560-MBGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB数： | 2400 |
| 逻辑元件/单元数： | 10800 |
| RAM 位总计： | 573440 |
| 输入/输出数： | 404 |
| 门数： | 129600 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 560-LBGA，金属 |
| 供应商设备封装： | 560-MBGA（42.5x42.5） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
22
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
1x Clock Outputs — CLK[0|90|180|270]
The 1x clock output pin CLK0 represents a delay-compen-
sated version of the source clock (CLKIN) signal. The CLK-
DLL primitive provides three phase-shifted versions of the
CLK0 signal while CLKDLLHF provides only the 180
phase-shifted version. The relationship between phase shift
and the corresponding period shift appears in Table 13.
The timing diagrams in Figure 25 illustrate the DLL clock
output characteristics.
The DLL provides duty cycle correction on all 1x clock out-
puts such that all 1x clock outputs by default have a 50/50
duty cycle. The DUTY_CYCLE_CORRECTION property
(TRUE by default), controls this feature. In order to deacti-
vate
the
DLL
duty
cycle
correction,
attach
the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol. When duty cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
The DLL clock outputs can drive an OBUF, a BUFG, or they
can route directly to destination clock pins. The DLL clock
outputs can only drive the BUFGs that reside on the same
edge (top or bottom).
Locked Output — LOCKED
To achieve lock, the DLL might need to sample several thou-
sand clock cycles. After the DLL achieves lock, the
LOCKED signal activates. The DLL timing parameter sec-
tion of the data sheet provides estimates for locking times.
To guarantee that the system clock is established prior to
the device “waking up,” the DLL can delay the completion of
the device configuration process until after the DLL locks.
The STARTUP_WAIT property activates this feature.
Until the LOCKED signal activates, the DLL output clocks
are not valid and can exhibit glitches, spikes, or other spuri-
ous movement. In particular the CLK2X output appears as a
1x clock with a 25/75 duty cycle.
DLL Properties
Properties provide access to some of the Virtex-E series
DLL features, (for example, clock division and duty cycle
correction).
Duty Cycle Correction Property
The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,
use the duty-cycle corrected default, exhibiting a 50/50 duty
cycle. The DUTY_CYCLE_CORRECTION property (by
default TRUE) controls this feature. To deactivate the DLL
duty-cycle correction for the 1x clock outputs, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol.
Clock Divide Property
The CLKDV_DIVIDE property specifies how the signal on
the CLKDV pin is frequency divided with respect to the
CLK0 pin. The values allowed for this property are 1.5, 2,
2.5, 3, 4, 5, 8, or 16; the default value is 2.
Startup Delay Property
This property, STARTUP_WAIT, takes on a value of TRUE
or FALSE (the default value). When TRUE the device con-
figuration DONE signal waits until the DLL locks before
going to High.
Virtex-E DLL Location Constraints
As shown in Figure 26, there are four additional DLLs in the
Virtex-E devices, for a total of eight per Virtex-E device.
These DLLs are located in silicon, at the top and bottom of
the two innermost block SelectRAM columns. The location
constraint LOC, attached to the DLL symbol with the identi-
fier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S,
or DLL3P, controls the DLL location.
The LOC property uses the following form:
LOC = DLL0P
Table 13:
Relationship of Phase-Shifted Output Clock
to Period Shift
Phase (degrees)
Period Shift (percent)
00%
90
25%
180
50%
270
75%
Figure 25: DLL Output Characteristics
ds022_29_121099
CLKIN
CLK2X
CLK0
CLK90
CLK180
CLK270
CLKDV
CLKDV_DIVIDE=2
DUTY_CYCLE_CORRECTION=FALSE
CLK0
CLK90
CLK180
CLK270
DUTY_CYCLE_CORRECTION=TRUE
t
0
90 180 270
0
90 180 270
相关PDF资料 |
PDF描述 |
|---|---|
| XC4VLX80-10FF1148I | IC FPGA VIRTEX-4LX 1148FFBGA |
| XC4VLX80-11FFG1148C | IC FPGA VIRTEX-4 LX 80K 1148FBGA |
| XC4VLX80-10FFG1148I | IC FPGA VIRTEX-4 LX 80K 1148FBGA |
| XCV600E-8FG900C | IC FPGA 1.8V C-TEMP 900-FBGA |
| XCV600E-7FG900I | IC FPGA 1.8V I-TEMP 900-FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XCV405E-7BG676C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG676I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG900C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG900I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7FG404C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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