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参数资料
| 型号： | XQ4013E-3HQ240N |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 125 MHz, PQFP240 |
| 封装： | PLASTIC, QFP-240 |
| 文件页数： | 13/36页 |
| 文件大小： | 294K |
| 代理商： | XQ4013E-3HQ240N |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
2-62
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
R
XQ4028EX Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature)
Global Buffer Switching Characteristics.
XQ4028EX Horizontal Longline Switching Characteristic Guidelines
Symbol
Description
-4
Units
Max
TGLS
From pad through Global Low Skew buffer, to any clock K
9.2
ns
TGE
From pad through Global Early buffer, to any clock K in same quadrant
5.7
ns
Symbol
Description
-4
Units
Max
TBUF Driving a Horizontal Longline
TIO1
I going High or Low to horizontal longline going High or Low, while T is Low. Buffer is
constantly active.
13.7
ns
TON
T going Low to horizontal longline going from resistive pull-up or floating High to active Low.
TBUF configured as open-drain or active buffer with I = Low.
14.7
ns
TBUF Driving Half a Horizontal Longline
THIO1
I going High or Low to half of a horizontal longline going High or Low, while T is Low. Buffer
is constantly active.
6.3
ns
THON
T going Low to half of a horizontal longline going from resistive pull-up or floating High to
active Low. TBUF configured as open-drain or active buffer with I = Low.
7.2
ns
Notes:
1.
These values include a minimum load of one output, spaced as far as possible from the activated pull-up(s). Use the static timing
analyzer to determine the delay for each destination.
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相关代理商/技术参数 |
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|---|---|
| XQ4013E-3PG191M | 制造商:XILINX 制造商全称:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013E-3PG191N | 制造商:XILINX 制造商全称:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4013E-3PG196M | 制造商:XILINX 制造商全称:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013E-3PG196N | 制造商:XILINX 制造商全称:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013E-4BG191M | 制造商:XILINX 制造商全称:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
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