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参数资料
| 型号： | XQ4013E-3HQ240N |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 125 MHz, PQFP240 |
| 封装： | PLASTIC, QFP-240 |
| 文件页数： | 3/36页 |
| 文件大小： | 294K |
| 代理商： | XQ4013E-3HQ240N |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
2-53
Product Specification
1-800-255-7778
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XQ4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000E devices unless otherwise noted.
Symbol
Single Port RAM
Size
-3
-4
Units
Min
Max
Min
Max
Write Operation
TWC
Address write cycle time
16x2
8.0
-
8.0
-
ns
TWCT
32x1
8.0
-
8.0
-
ns
TWP
Write Enable pulse width (High)
16x2
4.0
-
4.0
-
ns
TWPT
32x1
4.0
-
4.0
-
ns
TAS
Address setup time before WE
16x2
2.0
-
2.0
-
ns
TAST
32x1
2.0
-
2.0
-
ns
TAH
Address hold time after end of WE
16x2
2.0
-
2.5
-
ns
TAHT
32x1
2.0
-
2.0
-
ns
TDS
DIN setup time before end of WE
16x2
2.2
-
4.0
-
ns
TDST
32x1
2.2
-
5.0
-
ns
TDH
DIN hold time after end of WE
16x2
2.0
-
2.0
-
ns
TDHT
32x1
2.0
-
2.0
-
ns
Read Operation
TRC
Address read cycle time
16x2
3.1
-
4.5
-
ns
TRCT
32x1
5.5
-
6.5
-
ns
TILO
Data valid after address change (no Write Enable)
16x2
-
1.8
-
2.7
ns
TIHO
32x1
-
3.2
-
4.7
ns
Read Operation, Clocking Data into Flip-Flop
TICK
Address setup time before clock K
16x2
3.0
-
4.0
-
ns
TIHCK
32x1
4.6
-
6.1
-
ns
Read During Write
TWO
Data valid after WE goes active (DIN stable before WE)
16x2
-
6.0
-
10.0
ns
TWOT
32x1
-
7.3
-
12.0
ns
TDO
Data valid after DIN (DIN changes during WE)
16x2
-
6.6
-
9.0
ns
TDOT
32x1
-
7.6
-
11.0
ns
Read During Write, Clocking Data into Flip-Flop
TWCK
WE setup time before clock K
16x2
6.0
-
8.0
-
ns
TWCKT
32x1
6.8
-
9.6
-
ns
TDCK
Data setup time before clock K
16x2
5.2
-
7.0
-
ns
TDOCK
32x1
6.2
-
8.0
-
ns
Notes:
1.
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
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相关代理商/技术参数 |
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| XQ4013E-3PG191M | 制造商:XILINX 制造商全称:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013E-3PG191N | 制造商:XILINX 制造商全称:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
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| XQ4013E-3PG196N | 制造商:XILINX 制造商全称:XILINX 功能描述:QML High-Reliability FPGAs |
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