参数资料
型号: XR16C864IQ-F
厂商: Exar Corporation
文件页数: 49/51页
文件大小: 0K
描述: IC UART FIFO 128B QUAD 100QFP
标准包装: 66
特点: *
通道数: 4,QUART
FIFO's: 128 字节
规程: RS232,RS485
电源电压: 2.97 V ~ 5.5 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 100-BQFP
供应商设备封装: 100-QFP(14x20)
包装: 托盘
其它名称: 1016-1277
XR16C864
7
REV. 2.2.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
Factory Test Mode
If the IOR#, IOW# and CS# pins are all asserted (at a logic 0), the 864 will enter a Factory Test Mode.
CLKSEL
35
I
Baud-Rate-Generator Input Clock Prescaler Select for channels A-D. This input is only
sampled during power up or a reset. Connect to VCC for divide by 1 and GND for divide
by 4. MCR[7] can override the state of this pin following a reset or initialization. See MCR
bit-7 and
Figure 5 in the Baud Rate Generator section.
CHCCLK
42
I
This input provides the clock for UART channel C. An external 16X baud clock or the
crystal oscillator’s output, XTAL2, must be connected to this pin for normal operation.
This input may also be used with MIDI (Musical Instrument Digital Interface) applications
when an external MIDI clock is provided.
RESET
(RESET#)
43
I
When 16/68# pin is at logic 1 for Intel bus interface, this input becomes the Reset pin
(active high). In this case, a 40 ns minimum logic 1 pulse on this pin will reset the internal
registers and all outputs. The UART transmitter output will be held at logic 1, the receiver
input will be ignored and outputs are reset during reset period (
Table 19). When 16/68#
pin is at a logic 0 for Motorola bus interface, this input becomes Reset# pin (active low).
This pin functions similarly, but instead of a logic 1 pulse, a 40 ns minimum logic 0 pulse
will reset the internal registers and outputs.
VCC
10, 61,
86
Pwr
2.97V to 5.5V power supply. All input pins, except XTAL1, are 5V tolerant.
GND
20, 46,
71, 96
Pwr
Power supply common, ground.
Pin Description
NAME
100-QFP
PIN #
TYPE
DESCRIPTION
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