参数资料
| 型号： | XR16C864IQ-F |
| 厂商： | Exar Corporation |
| 文件页数： | 7/51页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 128B QUAD 100QFP |
| 标准包装： | 66 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 128 字节 |
| 规程： | RS232，RS485 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-QFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 1016-1277 |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页
XR16C864
15
REV. 2.2.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
2.13
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 128 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.13.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 128 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transm it Data Shift Register
(TS R)
Data Byte
THR Interrupt (IS R bit-1) falls
below the program m ed Trigger
Level and then when becom es
em pty. FIFO is Enabled by FCR
bit-0=1
RX FIFO
16X Clock
Auto CTS Flow Control (CTS # pin)
A uto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
T XF IF O 1
T HR
相关PDF资料 |
PDF描述 |
|---|---|
| XR16L2450IJ-F | IC UART FIFO 1B DUAL 44PLCC |
| XR16L2550IJ-F | IC UART FIFO 16B DUAL 44PLCC |
| XR16L2551IM-F | IC UART FIFO 16B DUAL 48TQFP |
| XR16L2552IJ-F | IC UART FIFO 16B DUAL 44PLCC |
| XR16L2750IJ-F | IC UART FIFO 64B DUAL 44PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16C864IQTR-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16C872 | 制造商:EXAR 制造商全称:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER |
| XR16C872CQ | 制造商:EXAR 制造商全称:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER |
| XR16C872IQ | 制造商:EXAR 制造商全称:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER |
| XR16L2450 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.25V TO 5.5V DUART |
发布紧急采购，3分钟左右您将得到回复。