参数资料
型号: XR16L2450IJ-F
厂商: Exar Corporation
文件页数: 2/30页
文件大小: 0K
描述: IC UART FIFO 1B DUAL 44PLCC
标准包装: 27
特点: *
通道数: 2,DUART
FIFO's: 1 字节
规程: RS232
电源电压: 2.25 V ~ 5.5 V
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 管件
XR16L2450
xr
2.25V TO 5.5V DUART
REV. 1.1.1
10
2.11
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 1 byte FIFO or Receive Holding
Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming
character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver
counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the
start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 2-4. Once the data is received, the error tags are immediately updated to
reflect the status of the data byte in RHR register. RHR will generate a receive data ready interrupt upon
receiving a character if IER bit-0 has been enabled.
2.11.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the 1 byte
receive FIFO that is 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. After the
RHR is read, LSR bits 2-4 willl immediately be updated to reflect the errors for the next character byte
transferred from the RSR.
FIGURE 6. RECEIVER OPERATION
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
相关PDF资料
PDF描述
XR16L2550IJ-F IC UART FIFO 16B DUAL 44PLCC
XR16L2551IM-F IC UART FIFO 16B DUAL 48TQFP
XR16L2552IJ-F IC UART FIFO 16B DUAL 44PLCC
XR16L2750IJ-F IC UART FIFO 64B DUAL 44PLCC
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