参数资料
| 型号： | XR16L2450IJ-F |
| 厂商： | Exar Corporation |
| 文件页数： | 6/30页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 1B DUAL 44PLCC |
| 标准包装： | 27 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 1 字节 |
| 规程： | RS232 |
| 电源电压： | 2.25 V ~ 5.5 V |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 管件 |
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XR16L2450
xr
2.25V TO 5.5V DUART
REV. 1.1.1
14
4.3.1
Interrupt Mode Operation
When the receive interrupt (IER BIT-0 = 1) is enabled, the RHR interrupt (see ISR bit-2) status will reflect the
following:
A. The receive data available interrupts are issued to the host when there is a character in the RHR. It will be
cleared when the character has been read out of the RHR.
B. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the RHR is empty.
4.3.2
Polled Mode Operation
Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode
by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in the RHR.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the RHR may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the THR and TSR are empty.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[7:4]: Reserved
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 6, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
相关PDF资料 |
PDF描述 |
|---|---|
| XR16L2550IJ-F | IC UART FIFO 16B DUAL 44PLCC |
| XR16L2551IM-F | IC UART FIFO 16B DUAL 48TQFP |
| XR16L2552IJ-F | IC UART FIFO 16B DUAL 44PLCC |
| XR16L2750IJ-F | IC UART FIFO 64B DUAL 44PLCC |
| XR16L2751CMTR-F | IC UART FIFO 64B DUAL 48TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16L2450IM | 制造商:EXAR 制造商全称:EXAR 功能描述:2.25V TO 5.5V DUART |
| XR16L2450IM-0A-EB | 功能描述:UART 接口集成电路 Supports L2450 48 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16L2450IM-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16L2550 | 制造商:EXAR 制造商全称:EXAR 功能描述:LOW VOLTAGE DUART WITH 16-BYTE FIFO |
| XR16L2550_07 | 制造商:EXAR 制造商全称:EXAR 功能描述:LOW VOLTAGE DUART WITH 16-BYTE FIFO |
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