参数资料
| 型号： | XR16L2551IM-F |
| 厂商： | Exar Corporation |
| 文件页数： | 18/49页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B DUAL 48TQFP |
| 标准包装： | 250 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 16 字节 |
| 规程： | RS232，RS485 |
| 电源电压： | 2.25 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
| 其它名称： | XR16L2551IM-F-ND |
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XR16L2551
25
REV. 1.1.3
LOW VOLTAGE DUART WITH POWERSAVE
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of
the FIFO.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16L2551IMTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 16Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L2551IMTR-F |
| XR16L2552 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| XR16L2552IJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16L2552IJ-0A-EB | 功能描述:UART 接口集成电路 Supports L2552 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16L2552IJ-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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