参数资料
| 型号： | XR16L788CQ-F |
| 厂商： | Exar Corporation |
| 文件页数： | 25/54页 |
| 文件大小： | 0K |
| 描述： | IC UART 64B 3.3V OCTAL 100QFP |
| 标准包装： | 66 |
| 特点： | * |
| 通道数： | 8 |
| FIFO's： | 64 字节 |
| 规程： | RS485 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-QFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 1016-1283 |
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XR16L788
31
REV. 1.2.3
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
4.4.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.
CTS#/DSR# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS/DSR flow
control enabled by EFR bit-7 and selection on MCR bit-2.
RTS#/DTR# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS/DTR flow
control enabled by EFR bit-6 and selection on MCR bit-2.
4.4.2
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xon or Xoff interrupt is cleared by a read to ISR register.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (default condition)
ISR[5:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 13). See “Section
4.4.1, Interrupt Generation:” on page 31 and “Section 4.4.2, Interrupt Clearing:” on page 31 for details.
TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF THE INTERRUPT+
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Received Data Ready)
3
0
1
0
RXRDY (Receive Data Time-out)
4
0
1
0
TXRDY (Transmitter Holding Register Empty)
5
0
MSR (Modem Status Register)
6
0
1
0
RXRDY (Received Xon/Xoff or Special character)
7
1
0
CTS#/DSR#, RTS#/DTR# change of state
X
0
1
None (default)
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| XR16L788CQTR-F | 功能描述:UART 接口集成电路 3.3V OCTAL UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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| XR16L788IQTR-F | 功能描述:UART 接口集成电路 3.3V OCTAL UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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