参数资料
型号: XR16V2551IL-0B-EB
厂商: Exar Corporation
文件页数: 8/49页
文件大小: 0K
描述: EVAL BOARD FOR V2551 32QFN
标准包装: 1
系列: *
FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Er
ror
T
ags
(16
-s
et
s)
E
rro
rT
ag
s
in
LS
R
b
its
4:2
Receive Data Characters
FIFO
Trigger=8
Example
: - RX FIFO trigger level selected at 8 bytes
(See Note Below)
Data fills to
14
Data falls to
4
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
16 bytes by 11-bit wide
FIFO
XR16V2551
16
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.3
2.13
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 10):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
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