参数资料
| 型号： | XR16V2650IL-F |
| 厂商： | Exar Corporation |
| 文件页数： | 23/47页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 32B DUAL 32QFN |
| 标准包装： | 490 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 32 字节 |
| 规程： | RS232，RS422 |
| 电源电压： | 2.25 V ~ 3.6 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 托盘 |
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XR16V2650
3
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME
32-QFN
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
18
19
20
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
2
1
32
31
30
29
28
27
3
2
1
48
47
46
45
44
I/O
Data bus lines [7:0] (bidirectional).
IOR#
14
19
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
12
15
I
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
7
10
I
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
CSB#
8
11
I
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
INTA
22
30
O
UART channel A Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
INTB
21
29
O
UART channel B Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
TXRDYA#
-
43
O
UART channel A Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A. See
Table 2. If it is not
used, leave it unconnected.
RXRDYA#
-
31
O
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
Table 2. If it is not
used, leave it unconnected.
TXRDYB#
-
6
O
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
Table 3. If it is not
used, leave it unconnected.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16V2650IM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16V2650IM-0B-EB | 功能描述:UART 接口集成电路 Supports V2650 48 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16V2650IM-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16V2650IMTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 32Byte FIFO 2.5V/3.3V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16V2650IMTR-F |
| XR16V2651 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE |
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