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参数资料
| 型号： | XR16V2652IL-0B-EB |
| 厂商： | Exar Corporation |
| 文件页数： | 7/48页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR V2652 32QFN |
| 标准包装： | 1 |
| 系列： | * |
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XR16V2652
15
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
2.13
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 10):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.14
Auto RTS Hysteresis
The V2652 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the selected RX trigger level. The RTS# pin will not be forced
HIGH (RTS off) until the receive FIFO reaches one trigger level above the selected trigger level in the trigger
table (Table 11). The RTS# pin will return LOW after the RX FIFO is unloaded to one level below the selected
trigger level. Under the above described conditions, the V2652 will continue to accept data until the receive
FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is asserted LOW (RTS On).
2.15
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 10):
Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (LOW), indicating more data may be sent.
TABLE 6: AUTO RTS (HARDWARE) FLOW CONTROL
RX TRIGGER LEVEL
INT PIN ACTIVATION
RTS# DEASSERTED (HIGH)
(CHARACTERS IN RX FIFO)
RTS# ASSERTED (LOW)
(CHARACTERS IN RX FIFO)
8
16
0
16
24
8
24
28
16
28
24
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16V2652IL32 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO |
| XR16V2652IL-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16V2652ILTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 32Byte FIFO 2.5V/3.3V 32-Pin QFN EP T/R 制造商:Exar Corporation 功能描述:XR16V2652ILTR-F |
| XR16V2750 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
| XR16V2750_07 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
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