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参数资料
| 型号： | XR16V654IJ-0A-EVB |
| 厂商： | Exar Corporation |
| 文件页数： | 6/58页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR16V654 68PLCC |
| 标准包装： | 1 |
| 系列： | * |
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XR16V654/654D
14
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.1
2.4
Channels A-D Internal Registers
Each UART channel in the V654 has a set of enhanced registers for controlling, monitoring and data loading
and unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a
user accessible scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the V654 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, FSTAT) that provide automatic RTS and CTS hardware flow control and automatic Xon/Xoff
software flow control.
All the register functions are discussed in full detail later
2.5
INT Ouputs for Channels A-D
The interrupt outputs change according to the operating mode and enhanced features setup. Table 3 and 4
2.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide
additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the
transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit
and receive FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFOs are enabled and the
DMA mode is disabled (FCR bit-3 = 0), the V654 is placed in single-character mode for data transmit or receive
operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by
TABLE 3: INT PIN OPERATION FOR TRANSMITTER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
INT Pin
LOW = a byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or
FIFO empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or
FIFO empty
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
INT Pin
LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16V654IJ-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16V654IJTR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 2.5V/3.3V 68-Pin PLCC T/R 制造商:Exar Corporation 功能描述:XR16V654IJTR-F |
| XR16V654IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16V654IL-0A-EVB | 功能描述:UART 接口集成电路 Supports V654 48 pin QFN, ISA Interface RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16V654IL-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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