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参数资料
型号： XR17C158IV-F
厂商： Exar Corporation
文件页数： 63/67页
文件大小： 0K
描述： IC UART PCI BUS OCTAL 144LQFP
标准包装： 60
特点： *
通道数： 8
FIFO's： 64 字节
规程： RS485
电源电压： 4.5 V ~ 5.5 V
带自动流量控制功能： 是
带IrDA 编码器/解码器： 是
带故障启动位检测功能： 是
带调制解调器控制功能： 是
安装类型： 表面贴装
封装/外壳： 144-LQFP
供应商设备封装： 144-LQFP（20x20）
包装： 托盘
其它名称： 1016-1646
XR17C158IV-F-ND
XRT99L00
xr
PCI BUS OCTAL UART
REV. 1.4.3
I
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS................................................................................................................................................1
FEATURES .....................................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1
FIGURE 2. PIN OUT OF THE DEVICE.................................................................................................................................................. 2
ORDERING INFORMATION
.................................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
FUNCTIONAL DESCRIPTION ...........................................................................................7
1.0 XR17C158 REGISTERS .........................................................................................................................8
FIGURE 3. THE XR17C158 REGISTER SETS..................................................................................................................................... 8
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................ 8
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ......................................................................................................... 9
1.2 DEVICE CONFIGURATION REGISTER SET ................................................................................................. 10
TABLE 2: XR17C158 DEVICE CONFIGURATION REGISTERS............................................................................................................. 11
TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT ................................................................................... 14
TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT............................................................................... 14
1.2.1 THE INTERRUPT STATUS REGISTER ..................................................................................................................... 15
FIGURE 4. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3 .................................................................................. 16
TABLE 5: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING..................................................................................................... 16
TABLE 6: UART CHANNEL [7:0] INTERRUPT CLEARING ................................................................................................................... 16
1.2.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-
00-00).............................................................................................................................................................................. 17
FIGURE 5. TIMER/COUNTER CIRCUIT............................................................................................................................................... 17
TABLE 7: TIMER CONTROL REGISTERS ...................................................................................................................................... 17
1.2.3 8XMODE [7:0] (DEFAULT 0X00)................................................................................................................................ 18
1.2.4 REGA [15:8] RESERVED ........................................................................................................................................... 18
1.2.5 RESET [23:16] (DEFAULT 0X00)............................................................................................................................... 18
1.2.6 SLEEP [31:24] - (DEFAULT 0X00)............................................................................................................................. 19
1.2.7 DEVICE IDENTIFICATION AND REVISION............................................................................................................... 19
1.2.8 REGB REGISTER ....................................................................................................................................................... 20
1.2.9 MULTI-PURPOSE INPUTS AND OUTPUTS .............................................................................................................. 20
1.2.10 MPIO REGISTER ...................................................................................................................................................... 20
FIGURE 6. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT ........................................................................................................... 21
2.0 CRYSTAL OSCILLATOR / BUFFER ...................................................................................................23
FIGURE 7. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 23
FIGURE 8. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE .......................................................................................... 23
3.0 TRANSMIT AND RECEIVE DATA .......................................................................................................24
3.1 DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS ............................................... 24
3.1.1 NORMAL RX FIFO DATA UNLOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700, 0X900, 0XB00, 0XD00, AND
0XF00 ............................................................................................................................................................................. 24
3.1.2 SPECIAL RX FIFO DATA UNLOADING AT LOCATIONS 0X180, 0X380, 0X580, 0X780, 0X980, 0XB80, 0XD80, 0XF80
25
3.1.3 TX FIFO DATA LOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700, 0X900, 0XB00, 0XD00, 0XF00 .......... 25
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN
8-BIT FORMAT ............................................................................................................................................... 26
TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE ............................................................ 26
4.0 UART ....................................................................................................................................................27
4.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 27
FIGURE 9. BAUD RATE GENERATOR ............................................................................................................................................... 27
TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING.......................................... 28
4.2 TRANSMITTER ............................................................................................................................................... 28
4.2.1 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 28
4.2.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 28
FIGURE 10. TRANSMITTER OPERATION IN NON-FIFO MODE ............................................................................................................ 29
4.2.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 29
4.2.4 AUTO RS485 OPERATION ........................................................................................................................................ 29
FIGURE 11. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ................................................................................... 30
4.3 RECEIVER ...................................................................................................................................................... 30
4.3.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ........................................................................................... 30
4.3.2 RECEIVER OPERATION IN NON-FIFO MODE ......................................................................................................... 31
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