参数资料
型号: XR17V258IV
厂商: Exar Corporation
文件页数: 10/69页
文件大小: 0K
描述: IC UART PCI BUS OCTAL 144LQFP
产品变化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
标准包装: 60
特点: *
通道数: 8
FIFO's: 64 字节
规程: RS485
电源电压: 3.3V,5V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
TABLE 7: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT
ADDRESS
REGISTER
BYTE 3 [31:24]
BYTE 2 [23:16]
BYTE 1 [15:8]
BYTE 0 [7:0]
0x080
-083
INTERRUPT (read-only)
INT3
INT2
INT1
INT0
0x084-087
TIMER (read/write)
TIMERMSB
TIMERLSB
TIMER (reserved)
TIMERCNTL
0x088-08B
ANCILLARY1 (read/write)
SLEEP
RESET
REGA
8XMODE
0x08C-08F
ANCILLARY2 (read-only)
MPIOINT
REGB
DVID
DREV
0x090-093
MPIO (read/write)
MPIOSEL
MPIOINV
MPIO3T
MPIOLVL
XR17V258
18
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.2
1.6.1
The Global Interrupt Register
The XR17V258 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is an 8-bit indicator representing all 8 channels with each bit
representing each channel from 0 to 7. This permits the interrupt service routine to quickly determine which
UART channels need servicing so that it can go to the appropriate UART channel interrupt service routines.
INT0 bit [0] represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or
modem port status requires service. Other bits in the INT0 register provide indication for the other channels
with bit [7] representing UART channel 7 respectively.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1, INT2 and INT3 registers provide the 24-bit interrupt
status for all 8 channels. bits [10:8] representing channel 0 and bits [31:29] representing channel 7
respectively. All 8 channel interrupts status are available with a single DWORD read operation. This feature
allows the host another method to quickly service the interrupts, thus reducing the service interval and host
bandwidth requirement.
GLOBAL INTERRUPT REGISTER (DWORD)
[default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:8]
INT0 [7:0]
All bits start up zero. A special interrupt condition is generated by the V258 upon awakening from sleep after all
eight channels were put to sleep mode earlier. This wake-up interrupt is cleared by a read to the INT0 register.
shows the 4-byte interrupt register and its make up.
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit [0] represents channel 0 and
bit [7] indicates channel 7. Logic 1 indicates the channel N [7:0] has called for service. The interrupt bit clears
after reading the appropriate register of the interrupting channel register, see Interrupt Clearing section.
The INT0 register provides individual status for each channel
INT0 Register
Individual UART Channel Interrupt Status
Ch-6
Ch-7
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
INT3, INT2 and INT1 [32:8] Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded
into 3 bits for receive, transmit, and status. bits [10:8] represent channel 0 and go up to channel 7 with
bits [31:29]. The 3-bit encoding and their priority order are shown below in Table 8. The Timer and MPIO
interrupts are for the device and therefore they exist within channel 0 space and not in other channel interrupt.
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