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参数资料
| 型号： | XR17V358IB-0A-EVB |
| 厂商： | Exar Corporation |
| 文件页数： | 43/68页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR17V358 |
| 产品培训模块： | PCIe UARTs UART Product Overview |
| 标准包装： | 1 |
| 主要目的： | 接口，UART |
| 嵌入式： | 否 |
| 已用 IC / 零件： | XR17V358 |
| 已供物品： | 板 |
| 相关产品： | 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA |
| 其它名称： | 1016-1293 |
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XR17V358
48
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
4.0 UART CONFIGURATION REGISTERS
4.1
Receive Holding Register (RHR) - Read only
4.2
Transmit Holding Register (THR) - Write only
4.3
Baud Rate Generator Divisors (DLM, DLL and DLD)
DLM[7:0], DLL[7:0] and DLD[3:0]
The Baud Rate Generator (BRG) generates the data rate for the transmitter and receiver. The rate is
programmed through registers DLM, DLL and DLD which are only accessible when LCR bit [7] is set to logic 1.
Refer to “Section 3.1, Programmable Baud Rate Generator with Fractional Divisor” on page 34 for more
details.
DLD[7]: RS-485 Polarity
Logic 0 = The Auto RS-485 Half-duplex direction control pin will be HIGH for TX and LOW for RX.
Logic 1 = The Auto RS-485 Half-duplex direction control pin will be LOW for TX and HIGH for RX.
DLD[6]: Multi-drop Mode
Logic 0 = Normal mode.
Logic 1 = Enable Multi-drop mode.
DLD[5]: XON/XOFF Parity Check
Logic 0 = XON/XOFF characters are valid flow control characters even if they have parity errors.
Logic 1 = XON/XOFF characters are not valid flow control characters if they have parity errors.
DLD[4]: Fast IR Mode
Logic 0 = If IR mode is enabled, IR pulsewidth will be 3/16th of bit time.
Logic 1 = If IR mode is enabled, IR pulsewidth will be 1/4th of bit time.
4.4
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) and also
encoded in INT (INT0-INT3) register in the Device Configuration Registers.
4.4.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR bit [0] = logic 1) and receive interrupts (IER bit [0] = logic 1) are enabled, the
RHR interrupts (see ISR bits [4:3]) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR bit [0]) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR17V358IB176-F | 功能描述:UART 接口集成电路 8 Channel PCIe UART w/256 Byte FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR17V358IB176-F | 制造商:Exar Corporation 功能描述:IC OCTAL UART 25MBPS 3.6V 176-BGA |
| XR17V358IB-E4-EVB | 功能描述:界面开发工具 Eval Board for XR17V358IB-E4 RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR17V358IB-E8-EVB | 功能描述:界面开发工具 Eval Board for XR17V358IB-E8 RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR1857SN | 制造商:Electro-Term/Hollingsworth 功能描述: |
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