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参数资料
| 型号： | XR19L200IL32-0B-EB |
| 厂商： | Exar Corporation |
| 文件页数： | 2/40页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR19L200 32QFN |
| 标准包装： | 1 |
| 系列： | * |
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XR19L200
10
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
2.10.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
2.10.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The Transmitter Empty Flag (LSR bit-6) is set when both the TSR and the FIFO become empty.
2.11
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. On the rising edge of RXD
(or falling edge of RX) of a start or a false start bit, an internal receiver counter starts counting at the 16X clock
rate. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled
and if it is still LOW it is validated as a start bit. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Each of the data, parity and stop bits is sampled at the middle of the bit to
prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading
the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately
updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt
FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X Clock
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
Transmit
FIFO
16X Clock
Auto Software Flow Control
Flow Control Characters
(Xoff1,2 and Xon1,2 Reg.)
THR Interrupt (ISR bit-1):
FIFO is Enabled by FCR bit-0=1
- When the TX FIFO falls below the
programmed Trigger Level, and
- When the TX FIFO becomes empty.
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相关代理商/技术参数 |
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| XR19L200IL32-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR19L202 | 制造商:EXAR 制造商全称:EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L202IL48 | 制造商:EXAR 制造商全称:EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L202IL48-0B-EB | 功能描述:界面开发工具 Supports L202 48 pin QFN,PCI Interface RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR19L202IL48-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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