参数资料
| 型号： | XR19L212IL48-F |
| 厂商： | Exar Corporation |
| 文件页数： | 21/52页 |
| 文件大小： | 0K |
| 描述： | IC UART/TXRX RS232 48QFN |
| 标准包装： | 260 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 64 字节 |
| 规程： | RS232 |
| 电源电压： | 3.3 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN-EP（7x7） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页
XR19L212
28
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 10 below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive
FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the
trigger level. Table 10 shows the complete selections. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
相关PDF资料 |
PDF描述 |
|---|---|
| XR19L220IL40-F | IC UART/TXRX RS232 40QFN |
| XR19L222IL64-F | IC UART/TXRX RS232 64QFN |
| XR19L400IL40-F | IC UART/TXRX RS485 40QFN |
| XR19L402IL48-F | IC UART/TXRX RS485 48QFN |
| XR20M1170IL24TR-F | IC UART FIFO I2C/SPI 64B 24QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XR19L212IL48TR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 64Byte FIFO 5V 48-Pin QFN EP T/R 制造商:Exar Corporation 功能描述:XR19L212IL48TR-F |
| XR19L220 | 制造商:EXAR 制造商全称:EXAR 功能描述:SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L220_07 | 制造商:EXAR 制造商全称:EXAR 功能描述:SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L220IL40 | 制造商:EXAR 制造商全称:EXAR 功能描述:SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L220IL40-0A-EB | 功能描述:界面开发工具 Supports L220 40 pin QFN, ISA Interface RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
发布紧急采购，3分钟左右您将得到回复。