参数资料
型号: XR20M1170IG24
厂商: Exar Corporation
文件页数: 11/56页
文件大小: 0K
描述: IC UART FIFO I2C/SPI 64B 24TSSOP
产品变化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
标准包装: 62
特点: *
通道数: 1,UART
FIFO's: 64 字节
规程: RS485
电源电压: 2.25 V ~ 3.6 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
XR20M1170
19
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
address, it does not have to anything. If the address does not match its slave address, then the receiver
should be disabled.
2.14.2
Auto Address Detection
Auto address detection mode is enabled when EFCR bit-0 = 1 and EFR bit-5 = 1. The desired slave address
will need to be written into the XOFF2 register. The receiver will try to detect an address byte that matches the
porgrammed character in the XOFF2 register. If the received byte is a data byte or an address byte that does
not match the programmed character in the XOFF2 register, the receiver will discard these data. Upon
receiving an address byte that matches the XOFF2 character, the receiver will be automatically enabled if not
already enabled, and the address character is pushed into the RX FIFO along with the parity bit (in place of the
parity error bit). The receiver also generates an LSR interrupt. The receiver will then receive the subsequent
data. If another address byte is received and this address does not match the programmed XOFF2 character,
then the receiver will automatically be disabled and the address byte is ignored. If the address byte matches
XOFF2, the receiver will put this byte in the RX FIFO along with the parity bit in the parity error bit.
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