参数资料
型号: XR20V2170IL40-F
厂商: Exar Corporation
文件页数: 21/49页
文件大小: 0K
描述: IC UART/TXRX I2C/SPI RS232 40QFN
标准包装: 490
特点: *
通道数: 1,UART
FIFO's: 64 字节
规程: RS232
电源电压: 2.97 V ~ 3.63 V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN 裸露焊盘(6x6)
包装: 托盘
其它名称: 1016-1478
XR20V2170IL40-F-ND
XR20V2170
28
I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
MCR[2]: OP1# / TCR and TLR Enable
OP1# is not available as an output pin on the V2170. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the MSR and TCR registers at address offset 0x6 and the SPR and TLR
registers at address offset 0x7. Table 12 and Table 13 below shows how these registers are accessed.
TABLE 12: REGISTER AT ADDRESS OFFSET 0X6
EFR[4] MCR[2] Register at Address Offset 0x6
0
X
Modem Status Register (MSR)
1
0
Modem Status Register (MSR)
1
Trigger Control Register (TCR)
TABLE 13: REGISTER AT ADDRESS OFFSET 0X7
EFR[4] MCR[2] Register at Address Offset 0x7
0
X
Scratchpad Register (SPR)
1
0
Scratchpad Register (SPR)
1
Trigger Level Register (TLR)
MCR[3]: OP2# Output
OP2# is not available as an output on the V2170 but can be controlled in internal loopback mode.
Logic 0 = OP2# output set HIGH(default).
Logic 1 = OP2# output set LOW.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the V2170 is programmed to use the Xon/Xoff flow control.
MCR[6]: Reserved
MCR[7]: Clock Prescaler Select (requires EFR bit-4=1 to write to this bit)
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
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