参数资料
型号: XR20V2170IL40-F
厂商: Exar Corporation
文件页数: 46/49页
文件大小: 0K
描述: IC UART/TXRX I2C/SPI RS232 40QFN
标准包装: 490
特点: *
通道数: 1,UART
FIFO's: 64 字节
规程: RS232
电源电压: 2.97 V ~ 3.63 V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN 裸露焊盘(6x6)
包装: 托盘
其它名称: 1016-1478
XR20V2170IL40-F-ND
XR20V2170
6
I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The V2170 can operate with either an I2C-bus interface or an SPI interface. The CPU interface is selected via
the I2C/SPI# input pin. The V2170 can operate with either an I2C-bus interface or an SPI interface. The CPU
interface is selected via the I2C/SPI# input pin.
2.1.1
I2C-bus Interface
The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-
bus interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial
clock and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to
400 kbps. The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW
when SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-
address that contains the address of the register to access. The V2170 responds to each write with an
acknowledge (SDA driven LOW by V2170 for one clock cycle when SCL is HIGH). If the TX FIFO is full, the
V2170 will respond with a negative acknowledge (SDA driven HIGH by V2170 for one clock cycle when SCL is
HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I2C-bus master contains a stop bit
(SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5 below. For complete details, see
the I2C-bus specifications.
FIGURE 3. I C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE (V2170)
SW
A
AP
SLAVE
ADDRESS
REGISTER
ADDRESS
nDATA
White block: host to UART
Grey block: UART to host
FIGURE 5. MASTER READS FROM SLAVE (V2170)
SW
A
AR
SLAVE
ADDRESS
REGISTER
ADDRESS
White block: host to UART
Grey block: UART to host
A
S
SLAVE
ADDRESS
nDATA
ANA
P
LAST DATA
2
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