参数资料
型号: XR21V1412IL32TR-F
厂商: Exar Corporation
文件页数: 26/32页
文件大小: 0K
描述: IC USB UART FIFO FULL SPD 32QFN
产品培训模块: XR21V141x Full-Speed USB UART Family
标准包装: 3,000
特点: *
通道数: 2,DUART
FIFO's: 128 字节,384 字节
规程: USB 2.0
电源电压: 2.97 V ~ 3.63 V
带自动流量控制功能:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 带卷 (TR)
配用: 1016-1301-ND - EVAL BOARD FOR XR21V1412IL
32
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2013 EXAR Corporation
Datasheet December 2013.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
XR21V1412
2-CH FULL-SPEED USB UART
REV. 1.3.0
REVISION HISTORY
DATE
REVISION
DESCRIPTION
June 2009
1.0.0
Released Datasheet.
September 2010
1.1.0
Clarified pin functionality, wide mode and low latency mode including registers /
blocks, clarified FLOW_CONTROL and GPIO_MODE register functionality.
April 2012
1.2.0
Updated ordering information, SDA/SCL pin types, modified GPIO0 pin names and
added LOOPBACK_CTL register and description. Updated LOWPOWER pin
description, bMaxPacketSize and DC electrical characterisitics. See PCN12-0305-
01 for more details.
December 2013
1.3.0
Added Windows driver versions, added absolute maximum tables, added ESD pro-
tection ratings, added QFN package center pad to pin descriptions, minor clarifica-
tions including requirement for even Product ID in Windows OS. [ECN:1402-05]
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