参数资料
型号: XRA1203IG24-F
厂商: Exar Corporation
文件页数: 12/17页
文件大小: 0K
描述: IC I/O EXPANDER I2C 16B 24TSSOP
标准包装: 62
接口: I²C,SM 总线
输入/输出数: 16
中断输出:
频率 - 时钟: 400kHz
电源电压: 1.65 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
其它名称: 1016-1715-5
XRA1203
4
16-BIT I2C/SMBUS GPIO EXPANDER WITH RESET
REV. 1.0.0
1.0 FUNCTIONAL DESCRIPTIONS
1.1
I2C-bus Interface
The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps.
The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is
HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that
contains the address of the register to access. The XRA1203 responds to each write with an acknowledge
(SDA driven LOW by XRA1203 for one clock cycle when SCL is HIGH). The last byte sent by an I2C-bus
master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5 below.
For complete details, see the I2C-bus specifications.
FIGURE 3. I C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE
SW
A
AP
SL AVE
AD D R ESS
CO M M A ND
BYT E
DA T A
BYT E
W h ite b lock: h o st to X R A 1 20 x
G rey block: X R A 12 0 x to h ost
FIGURE 5. MASTER READS FROM SLAVE
SW
A
AR
SLAVE
ADDRESS
COMMAND
BYTE
White block: host to XRA120x
Grey block: XRA120x to host
A
S
SLAVE
ADDRESS
nDATA
ANA
P
LAST DATA
2
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