参数资料
型号: XRD64L43AIV-F
厂商: Exar Corporation
文件页数: 3/20页
文件大小: 0K
描述: IC ADC 10B PAR 40MSPS DL 64LQFP
标准包装: 160
位数: 10
采样率(每秒): 40M
数据接口: 并联
转换器数目: 2
功率耗散(最大): 365mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
输入数目和类型: 2 个单端,单极;2 个差分,单极
其它名称: 1016-1638
XRD64L43AIV-F-ND
Preliminary
XRD64L43
11
Rev. P1.00
Differential Inputs
The XRD64L43 can be used in either differential or
single-ended input mode. For single-ended inputs, see
the Single-Ended Inputs Section. Differential inputs
reduce system noise by removing noise components
common at both input pins. Figure 5. is a simplified
diagram that is used as a common test circuit with our
XRD64L43ES application board. This circuit is used to
evaluate the dynamic performance of the XRD64L43
using differential inputs. Pin 16, DIFF should be held
high to select differential inputs.
Input A
Input B
VINA(+)
VCMO
VINA(-)
VINB(+)
VINB(-)
50
22
Transformer
Figure 5. Common Test Circuit for the
Differential Input Mode
SYNCO, Data Valid Delay and Latency
SYNCO is an output pin provided by the XRD64L43.
Valid data is available on the rising edge of SYNCO,
see Figure 6. The Latency for the XRD64L43 is 17
clock cycles.
Figure 6. SYNCO, Data Valid Delay and Latency
for the XRD64L43
Auto-Calibration
The XRD64L43 incorporates an auto-calibration cir-
cuit which continuously adjusts and matches the
offset and linearity of each ADC. This auto-calibra-
tion circuit is transparent to the user after the initial
4.2ms calibration (168,000 initial clock cycles).
Note: To avoid auto-calibration after power down, do
not disable CKIN. CKIN can be slowed down significantly
to save power without losing calibration.
CKIN
SYNCO
Valid Data
N
N-16
N-17
N-15
N+1
N+2
t
den=20ns
t
synco=2ns (typical)
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