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参数资料
| 型号： | XRD9836ACGTR-F |
| 厂商： | Exar Corporation |
| 文件页数： | 17/32页 |
| 文件大小： | 0K |
| 描述： | IC 16B CCD/CIS SIG PROC 48TSSOP |
| 标准包装： | 1,000 |
| 位数： | 16 |
| 通道数： | 3 |
| 功率（瓦特）： | 500mW |
| 电压 - 电源，模拟： | 3 V ~ 3.6 V |
| 电压 - 电源，数字： | 3 V ~ 3.6 V |
| 封装/外壳： | 48-TSSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 带卷 (TR) |
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XRD9836
xr
16-BIT PIXEL GAIN AFE
REV. 1.0.0
24
Delay
Registers
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DelayA
(10000)
DelayA
[7]
DelayA
[6]
DelayA
[5]
DelayA
[4]
DelayA
[3]
DelayA
[2]
DelayA
[1]
DelayA
[0]
default
1
0
DelayB
(10001)
DelayB
[7]
DelayB
[6]
DelayB
[5]
DelayB
[4]
DelayB
[3]
DelayB
[2]
DelayB
[1]
DelayB
[0]
default
0
DelayC
(10010)
DelayC
[7]
DelayC
[6]
DelayC
[5]
DelayC
[4]
DelayC
[3]
DelayC
[2]
DelayC
[1]
DelayC
[0]
default
0
DelayD
(10011)
DelayD
[7]
DelayD
[6]
DelayD
[5]
DelayD
[4]
DelayD
[3]
DelayD
[2]
DelayD
[1]
DelayD
[0]
default
0
DelayA[7:4] - Controls the OGI_DLY. These bits are used to program the timing delay of the ADCLK used to sample the
Offset-Gain-Inputs (OGI). Code 0000 is delay of 0ns, and code 1111 is 15ns. Default is 1000 = 7 ns. OGI_DLY should
be larger than VSAMP_OGI_DLY.
DelayA[3:0] - Controls the ADCO_DLY. These bits are used to program the timing delay of ADCO outputs in relation to
ADCLK. Code 0000 is delay of 0ns, and code 1111 is 15ns. Default is 0000 = 0ns. This is used to adjust setup and hold
times of the output, for the ASIC chip.
DelayB[7:4] - Controls the BSAMP_LEADING_EDGE_DLY. These bits set the delay for the leading edge of the internal
BSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayB[3:0] - Controls the BSAMP_TRAILING_EDGE_DLY. These bits set the delay for the trailing edge of the internal
BSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayC[7:4] - Controls the VSAMP_LEADING_EDGE_DLY. These bits set the delay for the leading edge of the internal
VSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayC[3:0] - Controls the VSAMP_TRAILING_EDGE_DLY. These bits set the delay for the trailing edge of the internal
VSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayD[7:4] - Controls the VSAMP_OGI_DLY. These bits set the delay for the internal VSAMP that is used to transfer
the OGI register data to the PGA & OFFSET control registers.
DelayD[3:0] - Controls the ADC_DLY. These bits set the delay of the internal clock used for ADC operation. Code 0000
is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
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