参数资料
型号: XRD98L59AIGTR
厂商: Exar Corporation
文件页数: 5/37页
文件大小: 0K
描述: IC CCD DIGITIZER 10BIT 28TSSOP
产品变化通告: Obsolescence Notification 15/Apr/2010
标准包装: 1,500
位数: 10
通道数: 1
电压 - 电源,模拟: 2.7 V ~ 3.6 V
电压 - 电源,数字: 2.7 V ~ 3.6 V
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 带卷 (TR)
13
Rev. 2.00
XRD98L59
PIXEL TIMING SBLK & SPIX
The timing required by the XRD98L59 to sample indi-
vidual pixel data from a CCD output is shown below in
Figure 6. The diagram shows the general relationship of
timing signals SBLK and SPIX to the CCD waveform.
Figure 6. CDS Timing Diagram - Proper Placement of Timing is
Critical to Image Quality, SDI=0011 0100 1100
*RST REJ is an internally generated signal.
Table 12. Event Table for CDS Timing (SDI=0011 0100 1100)
The XRD98L59 was designed to sample any analog CCD
waveform. In order to do this the timing signals need to
be referenced to the waveform itself, not to the CCD’s
timing generator.
Event
Action
RSTREJ
Disconnects CDS Inputs from Reset Noise
RSTREJ
Connects CDS Inputs
SBLK High
Sample Black Level
SPIX High
Sample Video Level
SBLK/SPIX Low Hold Video and Black Level
1
2
3
4
5
SBLK
SPIX
CCD
IN
RST REJ*
pixel black level
sample point
pixel video level
sample point
t
BK
t
VD
t
RST
Switch
Open
Reset
Pulse
Reset
Phase
Black
Reference
Phase
Video
Phase
1
2
3
4
3
4
55
1
Reset
Reject
Reset
Reject
Switch
Closed
Pixel N
Pixel N + 1
N-3
N-4
DB[9:0]
t
PIX
t
PW1
t
PW2
t
DL
t
DL
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