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参数资料
| 型号： | XRD98L62EVAL |
| 厂商： | Exar Corporation |
| 文件页数： | 8/37页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD XRD98L62 |
| 标准包装： | 1 |
| 系列： | * |
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XRD98L62
16
Rev. P2.00
Preliminary
RBenable RBreg
8
RBreg
7
RBreg
6
RBreg
5
Rbreg
4
RBreg
3
RBreg
2
RBreg
1
RBreg
0
Selected Register
0
xxxxxxxxx
none (ADC data output)
1
000000000
Gain
1
000000001
Offset
1
000000010
Calibration
1
000000011
Wait A
1
000000100
Wait B
1
000000101
OB Lines
1
000000110
CDAC
1
000000111
FDAC
1
000001000
Control
1
000001001
Polarity
1
000001010
Clock
1
000001011
Delay A
1
000001100
Delay B
1
000001101
DAC0
1
000001110
DAC1
1
000111110
ReadBack
1
000111111
Reset
1
0
1
xxxxxx
FDAC output from Cal. logic
1
0
1
0
xxxxxx
CDAC output from Cal. logic
1
0
1
xxxxxx
Avg. output from Cal logic
Serial Interface Read Back
The readback function is used to view the content of
the serial interface registers as well as several key
registers in the calibration logic. Readback is enabled
by writing a 1 to the RBenable bit of the Readback
register, bit D9 of register 62.
In the readback mode, the content of the selected
register is output on the 10 MSBs of the ADC output
bus pins DB[11:2]. As long as valid clocks and CCD
signal are applied, the calibration will continue to
function properly during readback (internally the ADC
data is still sent to the calibration logic).
Registers are selected for readback by writing to the
RBreg[8:0] bits in the Readback register, bits D8 to D0
of register 62. If RBreg[8:6]=000, then RBreg[5:0] are
used to address the serial interface registers. Cur-
rently only register addresses 0 to 14, 62 and 63 are
defined. If RBreg[8:6]
≠000, then RBreg[5:0] are ig-
nored and RBreg[8:6] are used to address registers in
the calibration logic. Currently only three calibration
registers are accessible.
Table 2. Read-back Register Selection
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