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| 型号： | XRT7300IV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 43/55页 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 SGL 44TQFP |
| 标准包装： | 160 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 1/1 |
| 规程： | DS3，E3，STS-1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LQFP |
| 供应商设备封装： | 44-TQFP（10x10） |
| 包装： | 托盘 |
| 其它名称： | 1016-1635 XRT7300IV-F-ND |
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XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.2
44
5.1.3
Command Register - CR2
Bit D4 - DECODIS (B3ZS/HDB3 Decoder-Disable)
This Read/Write bit-field is used to either enable or
disable the B3ZS/HDB3 Decoder in the XRT7300.
Writing a “1” to this bit-field disables the B3ZS/HDB3
Decoder. Writing a “0” to this bit-field enables the
B3ZS/HDB3 Decoder.
NOTE: This Decoder performs HDB3 Decoding if the
XRT7300 is operating in the E3 Mode. Otherwise it per-
forms B3ZS Decoding.
Bit D3 - ENCODIS (B3ZS/HDB3 Encoder-Disable)
This Read/Write bit-field is used to enable or disable
the B3ZS/HDB3 Encoder in the XRT7300.
Writing a “1” to this bit-field disables the B3ZS/HDB3
Encoder. Writing a “0” to this bit-field enables the
B3ZS/HDB3 Encoder.
NOTE: This Encoder performs HDB3 Encoding if the
XRT7300 is operating in the E3 Mode. Otherwise, it per-
forms B3ZS Encoding.
Bit D2 - ALOSDIS (Analog LOS Disable)
This Read/Write bit-field is used to disable the Analog
LOS Detector.
Writing a “0” to this bit-field enables the Analog LOS
Detector. Writing a “1” to this bit-field disables the
Analog LOS Detector.
NOTE: If the Analog LOS Detector is disabled, then the
RLOS input pin is only asserted by the DLOS (Digital LOS
Detector).
Bit D1 - DLOSDIS (Digital LOS Disable)
This Read/Write bit-field is used to disable the Digital
LOS Detector.
Writing a “0” to this bit-field enables the Digital LOS
Detector. Writing a “1” to this bit-field disables the
Digital LOS Detector.
NOTE: If the Digital LOS Detector is disabled, then the
RLOS input pin is only asserted by the ALOS (Analog LOS
Detector).
Bit D0 - REQDIS (Receive Equalization Disable)
This Read/Write bit-field is used to either enable or
disable the internal Receive Equalizer in the
XRT7300.
Writing a “0” to this bit-field enables the Internal
Equalizer. Writing a “1” to this bit-field disables the
Internal Equalizer.
5.1.4
Command Register - CR3
Bit D4 - RNRZ (Receive Binary Data)
This Read/Write bit-field is used to configure the
XRT7300 to output the received data from the Re-
mote Terminal in a binary or Dual-Rail format.
Writing a “1” to this bit-field configures the XRT7300
to output data to the Terminal Equipment in a Single-
Rail (binary) format via the RPOS output pin. The
RNEG is grounded. A “0” to this bit-field configures
the XRT7300 to output data to the Terminal Equip-
ment in a Dual-Rail format via both the RPOS and
RNEG output pins.
Bit D3 - LOSMUT (Recovered Data MUTing during
LOS Condition)
This Read/Write bit-field is used to configure the
XRT7300 to NOT output any recovered data while it
is declaring an LOS condition to the terminal equip-
ment.
Writing a “0” to this bit-field configures the chip to out-
put recovered data even while the XRT7300 is declar-
ing an LOS condition. Writing a “1” to this bit-field
configures the chip to NOT output the recovered data
while an LOS condition is being declared.
NOTE: In this mode, RPOS and RNEG is set to “0” asyn-
chronously.
Bit D2 - RCLK2/LCV (Receive Clock Output 2/Line
Code Violation)
This Read/Write bit-field is used to select the function
of pin 30 (RCLK2/LCV). Pin 30 can be configured to
function as the Line Code Violation output indicator or
as the additional Receive Clock Output (RCLK2).
Writing a “0” to this bit-field configures the pin to func-
tion as the Line Code Violation output pin. Writing a
“1” to this bit-field configures this pin to function as
the RCLK2 output pin.
Bit D1 - RCLK2INV (Invert RCLK2)
This Read/Write bit-field is used to configure the Re-
ceiver in the XRT7300 to output the recovered data
on either the rising edge or the falling edge of the
RCLK2 clock signal.
Writing a “0” to this bit-field configures the Receiver to
output the recovered data on the rising edge of the
RCLK2 output signal. Writing a “1” to this bit-field
configures the Receiver to output the recovered data
on the falling edge of the RCLK2 output signal.
Bit D0 - RCLK1INV (Invert RCLK1)
This Read/Write bit-field is used to configure the Re-
ceiver in the XRT7300 to output the recovered data
on either the rising edge or the falling edge of the
RCLK1 clock signal.
Writing a “0” to this bit-field configures the Receiver to
output the recovered data on the rising edge of the
RCLK1 output signal. Writing a “1” to this bit-field
configures the Receiver to output the recovered data
on the falling edge of the RCLK1 output signal.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT7300IVTR | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| XRT7300IVTR-F | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| XRT7302IV | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PCM Transceiver |
| XRT73L00 | 制造商:EXAR 制造商全称:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00A | 制造商:EXAR 制造商全称:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
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