参数资料
| 型号： | XRT75L00DIV |
| 厂商： | Exar Corporation |
| 文件页数： | 54/92页 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 SGL 52TQFP |
| 标准包装： | 96 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 1/1 |
| 规程： | DS3，E3，STS-1，SONET |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-LQFP |
| 供应商设备封装： | 52-TQFP（10x10） |
| 包装： | 托盘 |
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XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.2
53
Although the role of the H1, H2 and H3 bytes will be discussed in much greater detail in “Section 9.3, Jitter/
Wander due to Pointer Adjustments” on page 60. For now, we will simply state that the role of these bytes is
two-fold.
To permit a given PTE (Path Terminating Equipment) that is receiving an STS-1 data to be able to locate the
STS-1 SPE (Synchronous Payload Envelope) within the Envelope Capacity of this incoming STS-1 data
stream and,
To inform a given PTE whenever Pointer Adjustment and NDF (New Data Flag) events occur within the
incoming STS-1 data-stream.
9.2.1.1.2
The Envelope Capacity Bytes within an STS-1 Frame
In general, the Envelope Capacity Bytes are any bytes (within an STS-1 frame) that exist outside of the TOH
bytes. In short, the Envelope Capacity contains the STS-1 SPE (Synchronous Payload Envelope). In fact,
every single byte that exists within the Envelope Capacity also exists within the STS-1 SPE.
The only
difference that exists between the "Envelope Capacity" as defined in Figure 33 and Figure 34 above and the
STS-1 SPE is that the Envelope Capacity is aligned with the STS-1 framing boundaries and the TOH bytes;
whereas the STS-1 SPE is NOT aligned with the STS-1 framing boundaries, nor the TOH bytes.
The STS-1 SPE is an "87 byte column x 9 row" data-structure (which is the exact same size as is the Envelope
Capacity) that is permitted to "float" within the "Envelope Capacity". As a consequence, the STS-1 SPE (within
an STS-1 data-stream) will typically straddle across an STS-1 frame boundary.
9.2.1.1.3
The Byte Structure of the STS-1 SPE
As mentioned above, the STS-1 SPE is an 87 byte column x 9 row structure. The very first column within the
STS-1 SPE consists of some overhead bytes which are known as the "Path Overhead" (or POH) bytes. The
remaining portions of the STS-1 SPE is available for "user" data. The Byte Structure of the STS-1 SPE is
presented below in Figure 35.
FIGURE 34. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME
A1
B1
D1
H1
B2
D4
S1
D10
D7
C1
F1
D3
H3
K2
D6
E2
D12
D9
A2
E1
D2
H2
K1
D5
M0
D11
D8
Envelope Capacity
Bytes
Envelope Capacity
Bytes
3 Byte Columns
87 Byte Columns
9 Rows
The TOH Bytes
相关PDF资料 |
PDF描述 |
|---|---|
| MS27466T11B98SA | CONN RCPT 6POS WALL MT W/SCKT |
| MS27466E15A15S | CONN RCPT 15POS WALL MT W/SCKT |
| VE-21W-MX-F2 | CONVERTER MOD DC/DC 5.5V 75W |
| XRT83SH314IB | IC LIU T1/E1/J1 14CH 304TBGA |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT75L00DIV-F | 功能描述:外围驱动器与原件 - PCI 1-Ch DS3, E3, SONET RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT75L00DIVTR | 功能描述:时钟合成器/抖动清除器 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT75L00DIVTR-F | 功能描述:时钟合成器/抖动清除器 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT75L00ES | 功能描述:时钟合成器/抖动清除器 1CH T3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT75L00IV | 功能描述:外围驱动器与原件 - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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