参数资料
型号: XRT75L00DIVTR-F
厂商: Exar Corporation
文件页数: 27/92页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 SGL 52TQFP
标准包装: 1,000
类型: 线路接口装置(LIU)
驱动器/接收器数: 1/1
规程: DS3,E3,STS-1,SONET
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 52-LQFP
供应商设备封装: 52-TQFP(10x10)
包装: 带卷 (TR)
XRT75L00D
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
28
The Equalizer can either be “IN” or “OUT” by setting the REQEN pin “High” or “Low” (in Hardware Mode) or
setting the REQEN control bit to “1” or “0” (in Host Mode).
RECOMMENDATIONS FOR EQUALIZER SETTINGS:
The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/
STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable,
the Equalizer can be left “IN” by setting the REQEN pin to “High” (in Hardware Mode) or setting the REQEN
control bit to “1” (in Host Mode).
However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses (that does not meet the pulse
template requirements), it is recommended that the Equalizer be left “OUT” for cable length less than 300 feet
by setting the REQEN pin “Low” (in Hardware Mode) or by setting the REQEN control bit to “0” (in Host
Mode).This would help to prevent over-equalization of the signal and thus optimize the performance in terms of
better jitter transfer characteristics.
NOTE:
The results of extensive testing indicates that even when the Equalizer was left “IN” (REQEN = “HIGH”),
regardless of the cable length, the integrity of the E3 signal was restored properly over 0 to 12 dB cable
loss at Industrial Temperature.
The Equalizer also contain an additional 20 dB gain stage to provide the line monitoring capability of the
resistively attenuated signals which may have 20dB flat loss. This capability can be turned on by writing a “1” to
the RxMON bits in the control register or by setting the RxMON pin (pin 27) “High”.
5.1.1
Interference Tolerance:
For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error-free clock and
data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same
recommendation is being used. Figure 17 shows the configuration to test the interference margin for DS3/
STS1. Figure 18 shows the set up for E3.
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
SINE WAVE
GENERATOR
PATTERN
GENERATOR
223 - 1 PRBS
Μ
ATTENUATOR
DS3 = 22.368 MHz
STS-1 = 25.92 MHz
S
N
Cable Simulator
DUT
XRT75L00D
Test Equipment
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