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参数资料
| 型号： | XRT82D20IWTR |
| 厂商： | Exar Corporation |
| 文件页数： | 23/27页 |
| 文件大小： | 0K |
| 描述： | IC LIU EI SGL 28SOJ |
| 标准包装： | 1,000 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 1/1 |
| 规程： | E1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-BSOJ |
| 供应商设备封装： | 28-SOJ |
| 包装： | 带卷 (TR) |
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XRT82D20
4
REV. 1.0.8
SINGLE CHANNEL E1 LINE INTERFACE UNIT
11
DLoop
I
Digital Loop Back enable (active low):
Connect this pin to ground to enable Digital Local Loop-back.In Digital loop-back
mode, transmit input data after the encoder is looped back to the jitter attenuator (if
selected) and to the receive decoder. Input data at RTIP and RRing are ignored in
this mode. (internal pull-up). In this mode, the XRT82D20 can operate only as a jit-
ter attenuator.
12
ATM
I
Alarm Test Mode (Active-Low):
Connect this pin to ground to force ClkLOS, RLOS = 0 and LCV = 1 for testing with-
out affecting data transmission. (internal pull-up)
13
RAOS
I
Receive All Ones:
With this pin tied to High, an all “1’s” signal is inserted to the receiver output at
RPOS and RNEG/RData using MCLK as timing reference. This control has priority
over Digital Loop-back if both are enabled. (internal pull-down).
14
TAOS
I
Transmit All Ones:
With this pin tied High, an AMI encoded all “1’s” signal is sent to the transmit output
using MCLK as timing reference. This control has priority over Remote Loop-back if
both are enabled. (internal pull-down).
15
MClk
I
Master Clock Input:
This signal is an independent 2.048 MHz clock with accuracy better than + 50 ppM
and duty cycle within 40% to 60%. The function of MClk is to provide timing source
for the PLL clock recovery circuit, reference clock to insert all “1’s” data in the trans-
mit as well as receive paths. This signal must be available for the device to operate.
16
JATx/Rx
(DR/SR)
I
Jitter Attenuator Path Select:
With the jitter attenuator enabled, (pin 18 =”1”), tie this pin “High” to select the jitter
attenuator in the transmit path and tie it “Low” to select in the receive path. Data
input/output format is then controlled automatically by the status of the TNEG input.
If TNEG data is present the device operates in Dual-rail data mode.
Dual-Rail/Single-Rail Select:
With the jitter attenuator disabled, (pin 18 =”0”), tie this pin “High” to select Dual-Rail
data format and tie it “Low” to select Single-Rail data format. (internal pull-down)
17
DIGI
I
Digital Interface:
With this pin tied Low, input data at TPOS/TData and TNEG/CODE is active-high
and will be sampled by TClk on the falling edge, while active-high RPOS/RData and
RNEG output data are updated on the falling edge of RClk. See Figure 3 and 4 for
details.
With his pin tied high and in Dual-rail mode, transmit input accepts active-low
TPOS/TData and TNEG/CODE data and will be sampled by TClk on the falling
edge, while RPOS/RData and RNEG/LCV are active-low, data is updated on the
rising edge of RClk. (internal pull-down).
18
JAEN
I
Jitter Attenuator Enable (active high):
Connect this pin high to enable the jitter attenuation function. Jitter Attenuator Path
select is determined by the pin 16 setting. (internal pull-down)
19
TGND
-
Transmitter Supply Ground
20
TRing
O
Transmitter Ring Output:
Negative bipolar data output to the line.
21
TVDD
-
Transmit Positive Supply:
5.0 V + 5% or 3.3 V + 5%
PIN #SYMBOL
TYPE
DESCRIPTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT82D20IWTR-F | 功能描述:外围驱动器与原件 - PCI Single Ch E1 LIU RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT82L24 | 制造商:EXAR 制造商全称:EXAR 功能描述:QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT82L24A | 制造商:EXAR 制造商全称:EXAR 功能描述:QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT82L24AES | 功能描述:外围驱动器与原件 - PCI 4 CH E1 LIU SH RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT82L24AIV | 功能描述:外围驱动器与原件 - PCI Four ChannelE1 LIU RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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