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| 型号： | XRT82D20IWTR |
| 厂商： | Exar Corporation |
| 文件页数： | 5/27页 |
| 文件大小： | 0K |
| 描述： | IC LIU EI SGL 28SOJ |
| 标准包装： | 1,000 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 1/1 |
| 规程： | E1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-BSOJ |
| 供应商设备封装： | 28-SOJ |
| 包装： | 带卷 (TR) |
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XRT82D20
12
REV. 1.0.8
SINGLE CHANNEL E1 LINE INTERFACE UNIT
SYSTEM DESCRIPTION
The XRT82D20 is a single channel E1 transceiver that provides an electrical interface for 2.048Mbps
applications. XRT82D20 includes a receive circuit that converts an ITU-T G.703 compliant bipolar signal into a
TTL compatible logic levels. The receiver also includes an LOS (Loss of Signal) detection circuit. Similarly, in
the Transmit Direction, the Transmitter converts TTL compatible logic levels into a G.703 compatible bipolar
signal.
The XRT82D20 consists of both a Receive Section, Jitter Attenuator and Transmit Section; each of these
sections will be discussed below.
1.0
THE RECEIVE SECTION
At the receiver input, cable attenuated AMI signal can be coupled to the receiver using a capacitor or
transformer. The receive data first goes through the peak detector and data slicer for accurate data
recovery.The digital representation of the AMI signals go to the clock recovery circuit for timing recovery and
subsequently to the decoder (if selected) for HDB3 decoding before being output to the RPOS/RData and
RNEG/LCV pins. The digital data output can be in NRZ or RZ format depending the mode of operation
selected and with the option to be in dual-rail or single rail mode. Clock timing recovery of the line interface is
accomplished by means of a digital PLL scheme which has high input jitter tolerance.
The purpose of the Receive Output Interface block is to interface directly with the Receiving Terminal
Equipment.
The Receive Output Interface block outputs the data (which has been recovered from the
incoming line signal) to the Receive Terminal Equipment via the RPOS and RNEG output pins.
If the Receive Section of the XRT82D20 has received a Positive-Polarity pulse, via the RTIP and
RRing input pins, then the Receive Output Interface will output a pulse at the RPOS output pin.
Similarly, if the Receive Section of the XRT82D20 has received a Negative-Polarity pulse, via the RTIP and
RRing input pins, then the Receive Output Interface will output a pulse at the RNEG output pin.
1.1
JITTER ATTENUATOR
To reduce frequency jitter in the transmit clock or receive clock, a crystal-less jitter attenuator is provided. The
jitter attenuator can be selected either in the transmit or receive path or it can be disabled.
1.2
THE TRANSMIT SECTION
In general, the purpose of the Transmit Section (within the XRT82D20) is to accept TTL/CMOS level digital
data (from the Terminal Equipment), and to encode it into a format such that it can:
1. Be efficiently transmitted over coaxial- or twisted pair cable at the E1 data rate; and
2. Be reliably received by the Remote Terminal Equipment at the other end of the E1 data link.
3. Comply with the ITU-T G.703 pulse template requirements, for E1 applications
A 2.048 MHz clock is applied to the TClk input pin and NRZ data at the TPOS and TNEG input pins. The
Transmit Input Interface circuit will sample the data, at the TPOS and TNEG input pins, upon the falling edge of
TClk, as illustrated in Figure 8 below.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT82D20IWTR-F | 功能描述:外围驱动器与原件 - PCI Single Ch E1 LIU RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT82L24 | 制造商:EXAR 制造商全称:EXAR 功能描述:QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT82L24A | 制造商:EXAR 制造商全称:EXAR 功能描述:QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT82L24AES | 功能描述:外围驱动器与原件 - PCI 4 CH E1 LIU SH RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT82L24AIV | 功能描述:外围驱动器与原件 - PCI Four ChannelE1 LIU RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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