参数资料
型号: XRT83L38IB-F
厂商: Exar Corporation
文件页数: 7/87页
文件大小: 0K
描述: IC LIU T1/E1/J1 OCTAL 225BGA
标准包装: 84
类型: 线路接口装置(LIU)
驱动器/接收器数: 8/8
规程: T1,E1,J1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 225-BGA
供应商设备封装: 225-BGA(19x19)
包装: 托盘
XRT83L38
12
REV. 1.0.2
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
RDY_DTACK
EQC4
A6
O
I
Ready Output (Data Transfer Acknowledge Output) - Host mode
Intel bus timing: RDY is asserted “High” to indicate the device has completed a
read or write operation.
Motorola bus timing: DTACK is asserted “Low” to indicate the device has com-
pleted a read or write cycle.
Equalizer Control Input pin 4 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out.
NOTE: Internally pulled “Low” with a 50k
Ω resistor.
PTS1
PTS2
RCLKE
TCLKE
J16
L15
J16
L15
I
Microprocessor Type Select Input Pins - Host Mode:
Microprocessor Type Select Input Bit 1
Microprocessor Type Select Input Bit 2
Receive Clock Edge - Hardware mode
Transmit Clock Edge - Hardware mode
NOTE: These pins are internally pulled “Low” with a 50k
Ω resistor.
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
LOOP1_4
LOOP0_4
LOOP1_5
LOOP0_5
LOOP1_6
LOOP0_6
LOOP1_7
LOOP0_7
T7
U7
V7
V8
V9
U8
U9
R7
T7
U7
V7
V8
V9
U8
U9
R7
I/O
Microprocessor Read/Write Data Bus Pins - Host mode
Data Bus[7]
Data Bus[6]
Data Bus[5]
Data Bus[4]
Data Bus[3]
Data Bus[2]
Data Bus[1]
Data Bus[0]
Loop-back Control Pins, Bits [1:0] Channel_[7:4] - Hardware Mode
Pins 67-74 and 173-180 control which Loop-Back mode is selected per channel.
NOTE: Internally pulled “Low” with a 50k
Ω resistor for all channels.
SIGNAL NAME
LEAD #TYPE
DESCRIPTION
μ PTS2
μ PTS1
0
1
0
μP Type
68 HC11, 8051, 80C188 (async.)
Motorola 68K (async.)
Intel x86 (sync.)
Motorola 860 (sync.)
1
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