参数资料
| 型号： | XRT83VSH38IB |
| 厂商： | Exar Corporation |
| 文件页数： | 43/76页 |
| 文件大小： | 0K |
| 描述： | IC LIU SH T1/E1/J1 8CH 225BGA |
| 标准包装： | 84 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 8/8 |
| 规程： | T1，E1，J1 |
| 电源电压： | 3.14 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 225-BGA |
| 供应商设备封装： | 225-BGA（19x19） |
| 包装： | 托盘 |
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XRT83VSH38
45
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.9
6.4
Intel Mode Programmed I/O Access (Asynchronous)
If the LIU is interfaced to an Intel type P, then it should be configured to operate in the Intel mode. Intel type
Read and Write operations are described below.
Intel Mode Read Cycle
Whenever an Intel-type P wishes to read the contents of a register, it should do the following.
1.
Place the address of the target register on the address bus input pins ADDR[7:0].
2.
While the P is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
P and the LIU microprocessor interface block.
3.
Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4.
The P should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5.
Next, the P should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action also enables the bi-directional data bus output drivers of the LIU.
6.
After the P toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the P that the data is available to be read by the P, and that it is ready for the next com-
mand.
7.
After the P detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
NOTE: ALE can be tied “High” if this signal is not available.
The Intel Mode Write Cycle
Whenever an Intel type P wishes to write a byte or word of data into a register within the LIU, it should do the
following.
1.
Place the address of the target register on the address bus input pins ADDR[7:0].
2.
While the P is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
P and the LIU microprocessor interface block.
3.
Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4.
The P should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5.
The P should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus DATA[7:0].
6.
Next, the P should indicate that this current bus cycle is a Write operation by toggling the WR input pin
"Low". This action also enables the bi-directional data bus input drivers of the LIU.
7.
After the P toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the P that the data has been written into the internal register location, and that it is ready
for the next command.
NOTE: ALE can be tied “High” if this signal is not available.
The Intel Read and Write timing diagram is shown in Figure 35. The timing specifications are shown in
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| XRT83VSH38IB-F | 功能描述:外围驱动器与原件 - PCI 8 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83VSH38IB-F | 制造商:Exar Corporation 功能描述:T1/E1 LIU IC |
| XRT84L38 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER |
| XRT84L38_06 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER |
| XRT84L38IB | 功能描述:网络控制器与处理器 IC 8 Ch T1/E1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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