参数资料
| 型号： | XRT91L31IQ |
| 厂商： | Exar Corporation |
| 文件页数： | 7/41页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 8BIT 64QFP |
| 标准包装： | 160 |
| 类型： | 收发器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | LVCMOS，LVPECL，LVTTL |
| 输出： | LVCMOS，LVPECL，LVTTL |
| 电路数： | 1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622.08MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-FQFP |
| 供应商设备封装： | 64-PQFP（10x10） |
| 包装： | 托盘 |
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XRT91L31
15
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.0
RECEIVE SECTION
The receive section of XRT91L31 include the inputs RXIP/N, followed by the clock and data recovery unit
(CDR) and receive serial-to-parallel converter. The receiver accepts the high speed Non-Return to Zero (NRZ)
serial data at 622.08 Mbps or 155.52 Mbps through the input interfaces RXIP/N. The clock and data recovery
unit recovers the high-speed receive clock from the incoming scrambled NRZ data stream. The recovered
serial data is converted into an 8-bit-wide, 77.76 Mbps or 19.44 Mbps parallel data and presented to the
RXDO[7:0] parallel interface. This parallel interface is designed for Single-Ended LVTTL operation. A divide-
by-8 version of the high-speed recovered clock RXPCLKOP/N, is used to synchronize the transfer of the 8-bit
RXDO[7:0] data with the receive portion of the framer/mapper device. Upon initialization or loss of signal or
loss of lock, the external reference clock signal of 19.44 MHz or 77.76 MHz is used to start-up the clock
recovery phase-locked loop for proper operation. In certain applications, the CDR block on the XRT91L31 can
be disabled and bypassed by enabling the CDRDIS pin to permit the flexibility of using an externally recovered
receive clock thru the XRXCLKIP/N pins.
2.1
Receive Serial Input
The receive serial inputs are applied to RXIP/N and originate from an AC coupled environement (i.e. AC-
coupled SFP). A simplified block diagram is shown in Figure 3. Since this dievice has internal pull up/pull
down biasing resitors, a 100
line-to-line termination is the only resistor needed and must be installed as
close to the RXI pins as possible. See Applications note for further clarifications.
FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK
Ω
RXIP
RXIN
Optical Fiber
XRT91L31
STS-12/ STM-4
or
STS-3/ STM-1
Transceiver
XRXCLKIP
XRXCLKIN
( optional)
1k
Install terminators close to
RXIP and RXIN pins
Tie unused differential input pins
to VCC and GND
Internally AC coupled
SFP , Optical Module
100 Ohm
相关PDF资料 |
PDF描述 |
|---|---|
| XRT91L33IG-F | IC MULTIRATE CDR 20TSSOP |
| XRT91L34IV-F | IC MULTIRATE CDR QUAD 128LQFP |
| 07010 | CALIBRATION UNIT NIST STD WS&FG |
| 07200 | CHAIR COVER STATSHIELD |
| 07420 | BINDER 3RING DISSIPATIVE 3" |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L31IQ-F | 功能描述:网络控制器与处理器 IC 8-Bit TTL 3.3V temp -45 to 85C;UART RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| XRT91L31IQ-F | 制造商:Exar Corporation 功能描述:SONET Transceiver IC |
| XRT91L31IQTR | 功能描述:总线收发器 SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L31IQTR-F | 功能描述:总线收发器 SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L32 | 制造商:EXAR 制造商全称:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
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