参数资料
型号: XRT91L34IV-F
厂商: Exar Corporation
文件页数: 1/38页
文件大小: 0K
描述: IC MULTIRATE CDR QUAD 128LQFP
标准包装: 72
类型: 时钟和数据恢复(CDR),扇出缓冲器(分配),多路复用器
PLL:
主要目的: SONET/SDH,STS,STM
输入: LVDS,LVPECL
输出: LVDS,LVPECL
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 是/是
频率 - 最大: 622.08MHz
电源电压: 1.71 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x14)
包装: 托盘
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
OCTOBER 2007
REV. 1.0.1
GENERAL DESCRIPTION
The XRT91L34 is a fully integrated quad channel
multirate Clock and Data Recovery (CDR) device for
SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52
Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0
applications. The device provides Clock and Data
Recovery (CDR) function by synchronizing its on-chip
Voltage Controlled Oscillator (VCO) to the incoming
serial data stream. The device internally monitors
Loss of Lock (LOL) conditions and automatically
mutes recovered data upon Loss of Signal (LOS)
conditions.
CLOCK AND DATA RECOVERY OVERVIEW
The clock and data recovery (CDR) unit accepts the
high speed NRZ serial data from the LVDS or
Differential LVPECL receiver and generates a clock
that is the same frequency as the incoming data. The
CDR block uses a reference clock to train and
monitor its clock recovery PLL. All four channels
share a single 77.76MHz or 19.44MHz reference
clock. Upon startup, the PLL locks to the local
reference clock. Once this is achieved, the PLL
attempts to lock onto the incoming receive serial data
stream. Whenever the recovered clock frequency
deviates from the local reference clock frequency by
more than approximately ±500 ppm, the clock
recovery PLL will switch and lock back onto the local
reference clock and declare a Loss of Lock.
Whenever a Loss of Lock or a Loss of Signal event
occurs, the CDR will continue to supply a recovered
clock (based on the local reference) to the framer/
mapper device. When the SDEXT is de-asserted by
the optical module or when internal DLOS is
asserted, the receive serial data output will be forced
to a logic zero state for the entire duration that a LOS
condition is declared. This acts as a receive data
mute upon LOS function to prevent random noise
from being misinterpreted as valid incoming data.
When the SDEXT becomes active and the recovered
clock is determined to be within ±500 ppm accuracy
with respect to the local reference source and LOS is
no longer declared, the clock recovery PLL will switch
and lock back onto the incoming receive serial data
stream. Figure 1 shows the block diagram of the
XRT91L34.
FIGURE 1. BLOCK DIAGRAM OF XRT91L34
Channel 3
Channel 2
RXDO0P
RXDO0N
RXCLKO0P
RXCLKO0N
LOL0
Channel 0
LVDS/LVPECL
Output Drivers
CDR
RECVD-
DATAOUT
RECVD-
CLKOUT
Channel Control Block
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
LVDS/LVPECL
Input Drivers
RXDI0P
RXDI0N
RXDATAIN
RX LOOP
FILTER
SDEXT0
POL0
CDRDIS0
DATA0RATE0
DATA0RATE1
Global Control Block
RESET
INT
REFCLKP
HOST /HW
REFCLKN
1
0
CDRREFSEL
Channel 1
TTLREFCLK
19.44 / 77.76 MHz
100
OUTCFG
Serial Proccesor
Interface
SCLK
DLOSDIS /SDI
SDO
CS
XRT91L34
1
0
HOST MODE
ONLY
RCLKDIS0
LVDS/LVPECL LEVEL SELECT
DLOS
DLOSDIS
TEST
SDI
DLOSDIS
1
0
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