参数资料
| 型号： | XRT91L34IV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 37/38页 |
| 文件大小： | 0K |
| 描述： | IC MULTIRATE CDR QUAD 128LQFP |
| 标准包装： | 72 |
| 类型： | 时钟和数据恢复（CDR），扇出缓冲器（分配），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STS，STM |
| 输入： | LVDS，LVPECL |
| 输出： | LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622.08MHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-LQFP（14x14） |
| 包装： | 托盘 |
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XRT91L34
8
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
DLOSDIS
/SDI
LVTTL,
LVCMOS
I
39
DLOS (Digital Loss of Signal) Disable
Hardware Mode Disables internal DLOS monitoring and auto-
matic muting of RXDO[3:0]P/N recovered data output pins upon
DLOS detection. DLOS is declared when the incoming data
stream has no transition for more than 2.5
s. DLOS is cleared
when transitions are detected within a 128
s interval sliding
window.
"Low" = Monitor & Mute recovered data upon DLOS declaration
"High" = Disable internal DLOS monitoring
This pin is provided with an internal pull-down.
Host Mode This pin is functions as the microprocessor Serial
Data Input.
POL0
POL1
POL2
POL3
LVTTL,
LVCMOS
I
126
124
36
34
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"Low" = SDEXT is active "Low."
"High" = SDEXT is active "High."
NOTE: These pins have no function in Host Mode.
These pins are provided with internal pull-down.
SDEXT0
SDEXT1
SDEXT2
SDEXT3
LVTTL,
LVCMOS,
I
127
125
35
33
Signal Detect Input from Optical Module
When inactive, it will immediately declare a Loss of Signal
(LOS) condition and assert LOS register bit and mute the activ-
ity of the RXDO[3:0]P/N serial data output on the respective
channel.
"Active" = Normal Operation
"Inactive" = LOS Condition (SDEXT detects signal absence)
These pins are provided with internal pull-down.
REFCLKP
REFCLKN
LVDS,
Diff LVPECL
I
117
118
Reference Clock Input (77.76 MHz or 19.44 MHz)
This differential reference clock input will accept either a 77.76
MHz or a 19.44 MHz LVDS/Differential LVPECL clock source.
Pin CDRREFSEL determines the value used as the reference.
See Pin CDRREFSEL for more details. REFCLKP/N inputs are
internally biased to 1.2V via 15k
resistance. These pins are
equipped with a 100
line-to-line internal termination.
NOTE: In the event that TTLREFCLK LVTTL/LVCMOS input is
used instead of these differential inputs for clock
reference, the REFCLKP should be left unconnected
and REFCLKN should be tied to GND.
TTLREFCLK
LVTTL,
LVCMOS
I
120
TTL Reference Clock Input (77.76 MHz or 19.44 MHz)
This optional single-ended clock input reference can be used
instead of the differential REFCLKP/N input. It will accept
either a 77.76 MHz or a 19.44 MHz LVTTL clock source. Pin
CDRREFSEL determines the value used as the reference. See
Pin CDRREFSEL for more details.
NOTE:
In the event that REFCLKP/N differential inputs are
used instead of this LVTTL/LVCMOS input for clock
reference, the TTLREFCLK should be tied to ground.
This pin is provided with an internal pull-down.
NAME
LEVEL
TYPE
PIN
DESCRIPTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L34IVTR | 功能描述:网络控制器与处理器 IC 4 CH OC-12/STM4 OC-3/STM1 CDR RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| XRT91L34IVTR-F | 功能描述:网络控制器与处理器 IC 4 CH OC-12/STM4 OC-3/STM1 CDR RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| XRT91L80 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L80_0507 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L80ES | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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