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参数资料
| 型号： | YDA147 |
| 元件分类： | 音频／视频放大 |
| 英文描述： | 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP48 |
| 封装： | LEAD FREE, PLASTIC, SQFP-48 |
| 文件页数： | 6/36页 |
| 文件大小： | 1264K |
| 代理商： | YDA147 |
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YDA147
14
CATALOG No.:LSI-4DA147A61
·Sleep Function
YDA147 shifts into sleep mode when SLEEPN terminal goes to “L” level.
In the sleep mode, all functions stop and consumption current is minimized (ＩSLEEP).
When shifting into sleep mode during any protection mode, the protection mode is cancelled and PROTN terminal output
becomes Hi-Z state.
The digital amplifier output becomes Weak Low (a state grounded through a high resistance).
AVDD and VREF outputs are pulled down.
When the level at SLEEPN terminal is changed from “L” to “H” under the condition that the voltage at PVDDREG
terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation, the sleep
mode is cancelled and the state shifts into the normal operation state after the period of sleep recovery time (tWU).
·Mute Function
YDA147 shifts into mute mode when MUTEN terminal goes to “L” level.
In the mute mode, the digital amplifier output becomes Weak Low (a state grounded through a high resistance).
When the level at MUTEN terminal is changed from “L” to “H” under the condition that the voltage at PVDDREG
terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation and state of
SLEEPN terminal=H, the mute mode is cancelled and the state shifts into the normal operation state after the period of
mute recovery time (tMRCV).
·Clock Control Function
The setting of CKIN terminal controls the clock mode as shown below.
CKIN terminal Setting
Mode
CKOUT
L fixed
Internal Clock mode
Internal Clock (frequency: fCK) output
H fixed
Internal Clock (Spread clock) mode
Internal Clock (Spread Clock) frequency: (fCK)
output
Clock input
External Clock mode
CKIN input buffer output (frequency: fCKIN)
When CKIN terminal is held L or H level, internal clock mode is selected to generate a clock internally.
And, when CKIN terminal is held H level, Spread Clock function operates to reduce EMI.
When an external clock is input to CKIN terminal, its frequency should be fCKIN.
Do not use with CKIN terminal left open.
·Stereo/Monaural Switching Function
When INRP and INRM terminals (Rch input) are connected to AVDD, monaural mode is selected.
In the monaural mode, input signals input to INLP and INLM terminals (Lch input) are output from Lch and Rch digital
amplifiers.
With the monaural mode, parallel operation can be realized by connecting OUTPL to OUTPR and connecting OUTML
to OUTMR.
For details of connections, see “Single operation in monaural mode” (See page 24) in the “Examples of Application
Circuits.”
The switching between stereo and monaural modes should be performed under the following conditions.
·
Before PVDD power-on (lower than the PVDD shutdown threshold voltage)
·Digital Amplifier Pop Noise Reduction Function
Pop noise that may occur at the power-on, power-off, power-down, and power-down cancel operations, etc. is reduced by
minimizing an output offset voltage.
·Multi-chip Synchronization Function
The external clock synchronization function and clock output function are prepared and the use of master/slave
configuration realizes carrier clock synchronization.
When using it with multi chips synchronized, one is used as a master chip and the other is used as a slave chip. At this
time, connect CKOUT terminal of a master chip to CKIN terminal of a slave chip.
When using 3 chips (master/slave1/slave2), connect CKOUT terminal of a slave1 chip to CKIN terminal of a slave2 chip.
For details of connections, see “MASTER-SLAVE operation” (See page 26 and 27) in the “Examples of Application
Circuits.”
PVDD pins should be connected each other on a board.
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