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参数资料
| 型号： | YGV628B-VZ |
| 元件分类： | 显示控制器 |
| 英文描述： | 800 X 600 PIXELS CRT GRPH DSPL CTLR, PQFP176 |
| 封装： | LEAD FREE, PLASTIC, LQFP-176 |
| 文件页数： | 15/26页 |
| 文件大小： | 626K |
| 代理商： | YGV628B-VZ |
YGV628B
-22-
● Display Timing Signals (Measurement Condition : CL=20pF)
No.
Item
Symbol
Min
Typ
Max
Unit
Note
GCK1IN, GCK2IN : frequency
fGCKI
5
40
MHz
1
GCK1IN, GCK2IN : cycle time
tcGCKI
25
200
ns
2
GCK1IN, GCK2IN : clock high level width
twhGCKI
8
ns
3
GCK1IN, GCK2IN : clock low level width
twlGCKI
8
ns
4
HSIN_N, VSIN_N, DRI5-0, DGI5-0, DBI5-0: input
data setup time
tsDI
3
ns
5
HSIN_N,VSIN_N,DRI5-0, DGI5-0, DBI5-0: input
data hold time
thDI
1
ns
GCK1OUT: delay time
tdGCK1O
0
20
ns
6
GCK2OUT: delay time
tdGCK2O
0
20
ns
GCK1OUT : frequency
fGCK1O
5
40
MHz
GCK1OUT : cycle time
tcGCK1O
25
200
ns
GCK2OUT : frequency
fGCK2O
5
40
MHz
7
GCK2OUT : cycle time
tcGCK2O
25
200
ns
8
GCK1OUT, GCK2OUT : clock duty
tduGCKO
45
55
%
3
9
YS_N, CSYNC_N, VSYNC_N, BLANK_N,
DRO5-0, DGO5-0, DBO5-0: output delay time
tdDISP1
9
ns
10
YS_N, CSYNC_N, VSYNC_N, BLANK_N,
DRO5-0, DGO5-0,DBO5-0: output hold time
thDISP1
0
ns
Note 1)
Fulfill a condition
fSDCK
fGCK1O×2
Note 2)
Fulfill a condition
tcSDCK×2
tcGCK1O
Note 3)
In the cases of other than Analog synchronization
GCK1IN OR GCK2IN
Inputs
GCK1OUT OR GCK2OUT
Outputs
6
9
10
6
88
7
4
5
23
1
Inputs HSIN_N, VSIN_N, DRI5-0, DGI5-0, DBI5-0
Outputs YS_N, CSYNC_N, VSYNC_N, BLANK_N, DRO5-0, DGO5-0, DBO5-0
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