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参数资料
| 型号： | YMF754-V |
| 厂商： | Yamaha Corporation |
| 英文描述： | DS-1E |
| 中文描述： | 副秘书长至1E |
| 文件页数： | 15/60页 |
| 文件大小： | 305K |
| 代理商： | YMF754-V |
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YMF754
June 28, 1999
-22-
b2................WRST: AC’97 Warm Reset
This bit places the AC’97 in warm reset condition when the BIT_CLK signal on the AC’97 remains in
inactive state.
If this bit is set to “1”, it will automatically return to “0” after 1.3s time duration.
This
bit is valid only while the ACLS bit is set to “0”.
Except in this case, even if this bit is attempted to be
set to “1”, no warm reset will be generated (write operation of “1” remains disabled).
“0”: Normal
(default)
“1”: AC’97 Warm Reset
b3................ACLS: AC-Link Status
(Read Only)
This bit indicates whether or not the AC-link is active.
This bit is “1” when the AC-link remains in
active state (the BIT_CLK signal is active).
“0”: AC’97 Inactive
(default)
“1”: AC’97 Active
4A-4Bh: DS-1E Power Control 1
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
-
JSR
-
DPLL
-
DMC
b0................DMC: Disable Master Clock Oscillation
Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz).
“0”: Normal
(default)
“1”: Disable
b2................DPLL: Disable PLL Clock Oscillation
Setting this bit to “1” disables the oscillation of PLL.
“0”: Normal
(default)
“1”: Disable
b6................JSR: Joystick Reset
This bit controls reset of the flip-flop circuit following the analog comparator stage on the joystick port.
The Initial value is set to “0” immediately after power on reset or hardware reset.
“0”: Normal
(default)
“1”: Resets the flip-flop circuit following the analog comparator stage on the joystick port
b8................PR0: AC’97 Power Down Control 0
This bit controls the power state of the ADC and Input Mux in the Primary AC’97.
“0”: Normal
(default)
“1”: Power down
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