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参数资料
| 型号： | YMF754-V |
| 厂商： | Yamaha Corporation |
| 英文描述： | DS-1E |
| 中文描述： | 副秘书长至1E |
| 文件页数： | 17/60页 |
| 文件大小： | 305K |
| 代理商： | YMF754-V |
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YMF754
June 28, 1999
-24-
4C-4Dh: D-DMA Slave Configuration
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Base Address
EA
TS
CE
b0................CE: Channel Enable
This bit enables the Distributed DMA function.
“0”: Disable Distributed DMA
(default)
“1”: Enable Distributed DMA
b[2:1] ..........TS: Transfer Size
(Read Only)
These bits indicate the size of the DMA transfer. Since DS-1E supports only 8-bit DMA transfer, the bits
are hardwired to 00b.
b3................EA: Extended Address
(Read Only)
DS-1E does not support extended address mode.
This bit is hardwired to 0b.
b[15:4] ........Base Address : D-DMA Slave Base Address
These bits indicate the D-DMA slave base address.
4E-4Fh: DS-1E Power Control 2
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
-
PSHWV
PSIO
PSACL PSDIR
PSDIT
PSZV
PSSRC PSPCA PSJOY PSMPU
PSSB
PSFM
CMCD
b0................CMCD: CODEC Master Clock Disable
Setting this bit to “1” disables the oscillation of the CMCLK.
To stop a clock, when the CMCLK is
supplied to the AC’97, it is required that b13:PR5 bit of 4A-4Bh register is set to “1”.
(If the Secondary
AC’97 is used, it is also necessary that b5:SPR5 bit of 5A-5Bh register is set to “1”.)
“0”: Normal
(default)
“1”: Disable
b1................PSFM: Power Save FM Synthesizer
Setting this bit to “1” stops a clock supplied to the FM synthesizer block.
“0”: Normal
(default)
“1”: Disable
b2................PSSB: Power Save Sound Blaster
Setting this bit to “1” stops a clock supplied to the Sound Blaster block.
“0”: Normal
(default)
“1”: Disable
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