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参数资料
| 型号： | YMU759C-QZ |
| 元件分类： | 音频合成 |
| 英文描述： | TONE/MUSIC SYNTHESIZER, PQCC32 |
| 封装： | PLASTIC, QFN-32 |
| 文件页数： | 7/21页 |
| 文件大小： | 589K |
| 代理商： | YMU759C-QZ |
YMU759C
Preliminary
-15-
Read cycle
Note :
TACCA0 : The access time until D0 D7 are defined (0.65*IOVDD or 0.35*IOVDD) after A0 is defined (0.65*IOVDD).
Considers that /RD and /CS are defined beforehand (*1).
TACCCS : The access time until D0 D7 are defined (0.65*IOVDD or 0.35*IOVDD) after /CS is defined (0.35*IOVDD).
Considers that A0 and /RD are defined beforehand (*1).
TACCRD : The access time until D0 D7 are defined (0.65*IOVDD or 0.35*IOVDD) after /RD is defined (0.35*IOVDD).
Considers that A0 and /CS are defined beforehand (*1).
TRDH : The time (Hold time) until D0 D7 continue to output valid data after the timing (=0.35*IOVDD) /RD
becomes disable from enable under the condition that A0 and /CS secure sufficient hold time (*2).
TCDH : The time (Hold time) until D0 D7 continue to output valid data after the timing (=0.35*IOVDD) /CS becomes
disable from enable under the condition that A0 and /RD secure sufficient hold time (*2).
TADH : The time (Hold time) until D0 D7 continue to output valid data after the timing (=0.65*IOVDD or
0.35*IOVDD) A0 becomes disable from enable under the condition that /RD and /CS secure sufficient hold
time (*2).
TRDZ :
The time until D0
D7 become high impedance status after /RD becomes disable (=0.65*IOVDD) under the
condition that A0 and /CS secure sufficient hold time (*2).
TCDZ :
The time until D0
D7 become high impedance status after /CS becomes disable (=0.65*IOVDD) under the
condition that A0 and /RD secure sufficient hold time (*2).
TADZ : The time until D0 D7 become high impedance status after A0 becomes disable (=0.35*IOVDD) under the
condition that /RD and /CS secure sufficient hold time (*2).
■ Measurement point
VIH = 0.65*IOVDD
VIL = 0.35*IOVDD
VOH = 0.65*IOVDD
VOL = 0.35*IOVDD
■ Input condition at measurement
VIH = 0.8*IOVDD
VIL = 0.2*IOVDD
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