参数资料
型号: YSS912C
厂商: Yamaha Corporation
英文描述: One chip LSI Consisting of Dolby Digital (AC-3) / Pro Logic decoder amd Sub DSP(含杜比系统(AC-3)/前置逻辑译码器和声音处理DSP的集成电路)
中文描述: 一个芯片LSI,杜比数字组成(交流- 3)/定向逻辑解码器的AMD小组的DSP(含杜比系统(交流- 3)/前置逻辑译码器和声音处理数字信号处理器的集成电路)
文件页数: 12/14页
文件大小: 142K
代理商: YSS912C
YSS912C
7
Format diagram for read/write timing
When /CS=1, the SO output becomes high-impedance.
* Be sure to set /CSB to “1” when making an access to the control register.
The sound field processing program used for Sub DSP is down-loaded by using the /CSB, SCK, and SI terminals.
Please refer to Application manual for the details of Sub DSP.
4. External Interface
RAMA0-16, RAMD0-7, RAMCEN, RAMOEN, RAMWEN
An external SRAM can be connected to Sub DSP.
5. General purpose I/O ports
OPORT0-7, IPORT0-7
OPORT0-7 terminals are output ports for general purpose.
Data written on the register (address 0x04) are outputted from these terminals.
IPORT0-7 terminals are input ports for general purpose.
Data inputted to these terminals can be read from the register (address 0x05).
6. Initial clear
/IC
This LSI requires initial clear when turning on the power.
7. LSI test terminals
TEST
Leave the test terminals open in normal use.
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