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参数资料
| 型号： | YSS912F |
| 英文描述： | Stratix GX FPGA 25K 16-FBGA |
| 中文描述： | 消费性IC |
| 文件页数： | 29/32页 |
| 文件大小： | 802K |
| 代理商： | YSS912F |
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YSS915
6
FUNCTIONS
1. Clock signal
XI, XISEL, PLLC
Operation of this LSI requires input of clock with frequency of 384 fs (fs : sampling frequency) or 256 fs to the XI
terminal.
Keep the XISEL terminal open when using with the 384 fs clock.(XISEL pin is pulled up internally.)
Pull down XISEL terminal to the digital ground through 4.7 k ohm resistor when using with the 256 fs clock.
The sampling frequency can be selected in the range from 32 kHz to 48 kHz.
The sampling frequency is specified with OPR register ($00).(The sampling frequency of fs = 32 or 48 kHz can be
specified only KP2V Extended mode.)
In addition, the thing that input 37MHz in XI by a maximum is possible in only through-mode.
Connect a resistor and capacitor to PLLC terminal as shown below for adjustment of PLL in the LSI.
2. Initial clear
/IC
This LSI requires initial clear at power on. The initial clear is performed by inputting "L" to /IC terminal.
Note ;
N = KP2 standard mode
E = KP2V extended mode
Sampling
XI input frequency
Available mode
frequency (fs)
384fs
256fs
(See Note.)
32.0 kHz
12.288
MHz
8.192
MHz
E
37.8 kHz
14.5152 MHz
9.6768 MHz
N,E
44.1 kHz
16.9344 MHz
11.2896 MHz
N,E
48.0 kHz
18.432
MHz
12.288
MHz
E
/IC
2msec min
PLLC
KP2V2
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