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参数资料
| 型号： | YSS943-VZ |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 封装： | LEAD FREE, PLASTIC, LQFP-144 |
| 文件页数： | 5/36页 |
| 文件大小： | 831K |
| 代理商： | YSS943-VZ |
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YSS944/943/940
13
Microprocessor Interface
External microprocessor or similar devices use this microprocessor interface (4-wire serial interface) to
perform the following tasks.
Access to registers
Firmware download to on-chip memory
(1) Register access
Registers are accessed in 16-bit units via the microprocessor interface. MISI is used to specify the register’s
address (7 bits: A6 to A0) and the read/write option (1 bit:R/W). During a write operation (R/W=L), data (8
bits: D7 to D0) is input to MISI and during a read operation (R/W=H) 8-bit data is output from the MISO pin.
The data to be written is stored in the register at the rising edge of MISCK during the last data bit (D7 in
figure).
The microprocessor interface’s sequence when accessing registers is shown below.
A0 A1 A2
A3 A4
A5 A6 R/W D0D1
D2D3
D4D5
D6
D7
Don't care
High-Z
A0 A1 A2
A3 A4
A5 A6 R/W
Don't care
High-Z
D0 D1
D2 D3
D4 D5
D6
D7
High-Z
MISO
MISCK
MISI
nMICS
During
write
operation
(R/W = L)
During
read
operation
(R/W = H)
Don't care
MISO
MISI
[Note]
MISO is in output mode only when nMICS is at low level and during the data (8 bits) output timing.
Otherwise, it is in high impedance (High-Z) mode and MISCK, MISI, and MISO can be shared for devices
that have a similar interface.
Registers can be accessed continuously while nMICS remains at low level. There is no need to
repeatedly set nMICS to high level.
Certain register settings enable nMICS to be shared by multiple LSIs.
Access to on-chip memory (firmware download) is performed by combining with control of writing to a
register
Operation during a hardware reset (when nIC is at low level):
During a hardware reset, the microprocessor interface does not function. Also, MISO is fixed at high
impedance (High-Z). When nIC is at low level, nMICS should be initialized to high level.
Interruption of access:
Access can be interrupted by setting nMICS to high level. The write operation prior to the 16th rising
edge of MISCK (MISI’s D7 data capture clock) described above becomes invalid. The MISO pin is set
to high impedance (High-Z).
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