参数资料
型号: ZL2008ALBFT
厂商: Intersil
文件页数: 16/42页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 100
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2008
TABLE 6. ZL2106 START-UP SEQUENCE
STEP #
1
STEP NAME
Power Applied
DESCRIPTION
Input voltage is applied to the ZL2008’s VDD pin
TIME DURATION
Depends on input supply ramp
time
2
3
4
5
Internal Memory Check
Multi-mode Pin Check
Device Ready
Pre-ramp Delay
The device will check for values stored in its internal memory. This step
is also performed after a Restore command.
The device loads values configured by the multi-mode pins.
The device is ready to accept an enable signal.
The device requires approximately 2ms following an enable signal and
Approx 5ms to 10ms (device will
ignore an enable signal or PMBus
traffic during this period)
-
Approximately 2ms
prior to ramping its output. Additional pre-ramp delay may be
configured using the SS pin.
SS Pin
TABLE 7. Soft-start Pin-strap Settings
Delay Time Ramp Time
(ms) (ms)
A PG delay period is defined as the time from when all conditions
within the ZL2008 for asserting PG are met to when the PG pin is
actually asserted. This feature is commonly used instead of using
an external reset controller to control external digital logic. By
LOW
OPEN
HIGH
2
5
10
2
5
10
default, the ZL2008 PG delay is set equal to the soft-start ramp
time setting. Therefore, if the soft-start ramp time is set to 10ms,
the PG delay will be set to 10ms. The PG delay may be set
independently of the soft-start ramp using the I 2 C/SMBus as
If the desired soft-start delay and ramp times are not one of the
values listed in Table 7, the times can be set to a custom value by
described in Application Note AN2033.
TABLE 8. SS Resistor Settings
connecting a resistor from the SS pin to SGND using the
appropriate resistor value from Table 8. The value of this resistor
is measured upon start-up or Restore and will not change if the
resistor is varied after power has been applied to the ZL2008.
See Figure 13 for typical connections using resistors.
ZL
R SS
FIGURE 13. SS Pin Resistor Connections
The soft-start delay and ramp times can also be set to custom
values via the I 2 C/SMBus interface. When the SS delay time is
set to 0ms, the device will begin its ramp-up after the internal
circuitry has initialized (approx. 2ms). When the soft-start ramp
period is set to 0ms, the output will ramp up as quickly as the
output load capacitance and loop settings will allow. It is
generally recommended to set the soft-start ramp to a value
greater than 500μs to prevent inadvertent fault conditions due to
excessive inrush current.
Power Good
The ZL2008 provides a Power Good (PG) signal that indicates the
output voltage is within a specified tolerance of its target level
and no fault condition exists. By default, the PG pin will assert if
the output is within
-10% of the target voltage. These limits and the polarity of the pin
may be changed via the I 2 C/SMBus interface. See Application
R SS
(k Ω )
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
82.5
Delay Time
(ms)
2
5
10
15
20
30
Ramp Time
(ms)
5
10
20
2
5
10
20
2
5
10
20
2
5
10
20
2
5
10
20
2
5
10
20
Note AN2033 for details.
16
FN6859.4
April 29, 2011
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