参数资料
型号: ZL2008ALBFT
厂商: Intersil
文件页数: 18/42页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 100
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2008
TABLE 11. Switching Frequency Resistor Settings
TABLE 12. Power Supply Requirements
R SYNC
(k Ω )
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
f SW
(kHz)
200
222
242
267
296
320
364
400
421
471
533
Parameter
Input voltage (V IN )
Output voltage (V OUT )
Output current (I OUT )
Output voltage ripple
(V orip )
Output load step (I ostep )
Output load step rate
Output deviation due to load step
Maximum PCB temp.
Desired efficiency
Other considerations
Range
3.0V to 14.0V
0.6V to 5.0V
0A to ~25A
< 3% of V OUT
< Io
+120°C
Various
Example Value
12V
1.2V
20A
1% of V OUT
50% of I o
10A/μs
± 50mV
+85°C
85%
Optimize for small
28.7
31.6
34.8
38.3
46.4
51.1
56.2
68.1
571
615
727
800
889
1000
1143
1333
size
DESIGN GOAL TRADE-OFFS
The design of the buck power stage requires several
compromises among size, efficiency, and cost. The inductor core
loss increases with frequency, so there is a trade-off between a
small output filter made possible by a higher switching frequency
and getting better power supply efficiency. Size can be decreased
by increasing the switching frequency at the expense of
efficiency. Cost can be minimized by using through-hole
inductors and capacitors; however these components are
physically large.
The switching frequency can also be set to any value between
200kHz and 1.33MHz using the I 2 C/SMBus interface. The
available frequencies below 1.4MHz are defined by f SW = 8MHz/N,
where the whole number N is 6 ≤ N ≤ 40. See Application Note
AN2033 for details.
To start the design, select a switching frequency based on
Table 13. This frequency is a starting point and may be adjusted
as the design progresses.
TABLE 13. Circuit Design Consideration
If a value other than f SW = 8MHz/N is entered using a PMBus
command, the internal circuitry will select the valid switching
frequency value that is closest to the entered value. For example,
if 810kHz is entered, the device will select 800kHz (N=10).
When multiple Zilker Labs devices are used together, connecting
Frequency Range
200kHz to 400kHz
400kHz to 800kHz
800kHz to 1.4MHz
Efficiency
Highest
Moderate
Lower
Circuit Size
Larger
Smaller
Smallest
the SYNC pins together will force all devices to synchronize with
each other. The CFG1 pin of one device must set its SYNC pin as
an output and the remaining devices must have their SYNC pins
set as Auto Detect.
Note: The switching frequency read back using the appropriate
PMBus command will differ slightly from the selected values in
Table 11. The difference is due to hardware quantization.
Power Train Component Selection
The ZL2008 is a synchronous buck converter that uses external
INDUCTOR SELECTION
The output inductor selection process must include several trade-
offs. A high inductance value will result in a low ripple current
(I opp ), which will reduce output capacitance and produce a low
output ripple voltage, but may also compromise output transient
load performance. Therefore, a balance must be struck between
output ripple and optimal load transient performance. A good
starting point is to select the output inductor ripple equal to the
expected load transient step magnitude (I ostep ):
MOSFETs, inductor and capacitors to perform the power
conversion process. The proper selection of the external
components is critical for optimized performance.
To select the appropriate external components for the desired
performance goals, the power supply requirements listed in
Table 12 must be known.
18
I opp = I ostep
(EQ. 4)
FN6859.4
April 29, 2011
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