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| 型号： | ZL2106ALCF |
| 厂商： | Intersil |
| 文件页数： | 13/29页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 36QFN |
| 标准包装： | 50 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.54 V ~ 5.5 V |
| 输入电压： | 4.5 V ~ 14 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 36-QFN（6x6） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
ZL2106
TABLE 3. ZL2106 START-UP SEQUENCE
STEP #
1
STEP NAME
Power Applied
DESCRIPTION
Input voltage is applied to the ZL2106’s VDD pins (VDDP and VDDS).
TIME DURATION
Depends on input supply ramp
time
2
Internal Memory Check The device will check for values stored in its internal memory. This step is also
performed after a Restore command.
Approx 5ms to 10ms (device will
ignore an enable signal or PMBus
3
4
5
Multi-mode Pin Check
Device Ready
Pre-ramp Delay
The device loads values configured by the multi-mode pins.
The device is ready to accept an enable signal.
The device requires approximately 2ms following an enable signal and prior to
traffic during this period)
-
Approximately 2ms
ramping its output. Additional pre-ramp delay may be configured using the SS pin.
TABLE 4. RESISTORS FOR SETTING OUTPUT VOLTAGE
R SET V OUT
(k Ω ) (V)
The resistor setting method can be used to set the output voltage to
levels not available in Table 2. To set V OUT using resistors, use Table
4 to select the resistor that corresponds to the desired voltage.
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
100
110
121
133
147
162
178
13
0.6
0.7
0.75
0.8
0.9
1.0
1.1
1.2
1.25
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
5.0
The output voltage may also be set to any value between 0.6V
and 5.0V using the I 2 C interface. See Application Note AN2033
for details.
Start-up Procedure
The ZL2106 follows a specific internal start-up procedure after
power is applied to the VDD pins (VDDP and VDDS). Table 3
describes the start-up sequence.
If the device is to be synchronized to an external clock source, the
clock frequency must be stable prior to asserting the EN pin. The
device requires approximately 5ms to 10ms to check for specific
values stored in its internal memory. If the user has stored values
in memory, those values will be loaded. The device will then
check the status of all multi-mode pins and load the values
associated with the pin settings.
Once this process is completed, the device is ready to accept
commands via the I 2 C/SMBus interface and the device is ready
to be enabled. Once enabled, the device requires approximately
2ms before its output voltage may be allowed to start its
ramp-up process. If a soft-start delay period less than 2ms has
been configured (using PMBus commands), the device will
default to a 2ms delay period. If a delay period greater than 2ms
is configured, the device will wait for the configured delay period
prior to starting to ramp its output.
After the delay period has expired, the output will begin to ramp
towards its target voltage according to the pre-configured soft-
start ramp time that has been set using the SS pin. It should be
noted that if the EN pin is tied to VDDP or VDDS, the device will
still require approximately 5ms to 10ms before the output can
begin its ramp-up as described in Table 3.
Soft-start Delay and Ramp Times
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to set the time required
for V OUT to ramp to its target value after the delay period has
expired. These features may be used as part of an overall inrush
current management strategy or to control how fast a load IC is
turned on. The ZL2106 gives the system designer several options
for precisely and independently controlling both the delay and
ramp time periods.
FN6852.6
February 20, 2013
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