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| 型号： | ZL6100ALAFT |
| 厂商： | Intersil |
| 文件页数： | 14/34页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ZL6100
TABLE 6. ZL6100 START-UP SEQUENCE
STEP
STEP NAME
DESCRIPTION
TIME DURATION
1
2
3
Power Applied
Internal Memory Check
Multi-mode Pin Check
Input voltage is applied to the ZL6100’s VDD pin Depends on input supply ramp time
The device will check for values stored in its
internal memory. This step is also performed after
Approx 5ms to 10ms (device will ignore an
a Restore command.
enable signal or PMBus traffic during this period)
The device loads values configured by the multi-
mode pins.
4
Device Ready
The device is ready to accept an enable signal.
-
5
Pre-ramp Delay
The device requires approximately 2ms following Approximately 2ms
an enable signal and prior to ramping its output.
Additional pre-ramp delay may be configured
using the Delay pins.
Soft-start Delay and Ramp Times
It may be necessary to set a delay from when an enable
signal is received until the output voltage starts to ramp to its
TABLE 8. SOFT-START RAMP SETTINGS
RAMP TIME
target value. In addition, the designer may wish to precisely
set the time required for V OUT to ramp to its target value after
the delay period has expired. These features may be used
as part of an overall inrush current management strategy or
to precisely control how fast a load IC is turned on. The
SS
LOW
OPEN
HIGH
(ms)
0
5
10
ZL6100 gives the system designer several options for
precisely and independently controlling both the delay and
ramp time periods.
The soft-start delay period begins when the EN pin is
asserted and ends when the delay time expires. The
soft-start delay period is set using the DLY (0, 1) pins.
Precise ramp delay timing reduces the delay time variations
but is only available when the appropriate bit in the
MISC_CONFIG register has been set. Please refer to
Application Note AN2033 for details.
The soft-start ramp timer enables a precisely controlled ramp
to the nominal V OUT value that begins once the delay period
has expired. The ramp-up is guaranteed monotonic and its
slope may be precisely set using the SS pin.
Note: When the device is set to 0ms ramp, it will attempt to
ramp as fast as the external load capacitance and loop
settings will allow. It is generally recommended to set the
soft-start ramp to a value greater than 500μs to prevent
inadvertent fault conditions due to excessive inrush current.
If the desired soft start delay and ramp times are not one of
the values listed in Tables 7 and 8, the times can be set to a
custom value by connecting a resistor from the DLY0 or SS
pin to SGND using the appropriate resistor value from
Table 9. The value of this resistor is measured upon start-up
or Restore and will not change if the resistor is varied after
power has been applied to the ZL6100. See Figure 12 for
typical connections using resistors.
TABLE 9. DLY AND SS RESISTOR SETTINGS
The soft start delay and ramp times can be set to standard
values according to Tables 7 and 8 respectively.
TABLE 7. SOFT-START DELAY SETTINGS
DLY0
DLY OR SS
(ms)
0
10
R DLY OR R SS
(k Ω )
10
11
DLY OR SS
(ms)
110
120
R DLY OR R SS
(k Ω )
28.7
31.6
LOW
(ms)
OPEN
(ms)
HIGH
(ms)
20
30
12.1
13.3
130
140
34.8
38.3
LOW
0
1
2
40
14.7
150
42.2
DLY1
OPEN
HIGH
5
50
10
100
20
200
50
60
16.2
17.8
160
170
46.4
51.1
Note: When the device is set to 0ms or 1ms delay, it will begin
its ramp up after the internal circuitry has initialized (~2ms).
70
80
90
19.6
21.5
23.7
180
190
200
56.2
61.9
68.1
14
100
26.1
FN6876.3
August 29, 2012
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