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参数资料
| 型号： | ZL6100EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 15/34页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD USB ZL6100 |
| 标准包装： | 1 |
| 系列： | * |
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ZL6100
The SYNC pin is a unique pin that can perform multiple
NC
R DLY
functions depending on how it is configured. The CFG pin is
used to select the operating mode of the SYNC pin as
shown in Table 10. Figure 13 illustrates the typical
connections for each mode.
ZL6100
TABLE 10. SYNC PIN FUNCTION SELECTION
CFG PIN SYNC PIN FUNCTION
R SS
LOW
OPEN
HIGH
SYNC is configured as an input
Auto Detect mode
SYNC is configured as an output
f SW = 400kHz
CONFIGURATION A: SYNC OUTPUT
FIGURE 12. DLY AND SS PIN RESISTOR CONNECTIONS
Note: Do not connect a resistor to the DLY1 pin. This pin is
not utilized for setting soft-start delay times. Connecting an
external resistor to this pin may cause conflicts with other
device settings.
The soft-start delay and ramp times can also be set to
custom values via the I 2 C/SMBus interface. When the SS
delay time is set to 0ms, the device will begin its ramp-up
after the internal circuitry has initialized (~2ms). When the
soft-start ramp period is set to 0ms, the output will ramp-up
as quickly as the output load capacitance and loop settings
will allow. It is generally recommended to set the soft-start
ramp to a value greater than 500μs to prevent inadvertent
fault conditions due to excessive inrush current.
Power-Good
The ZL6100 provides a Power-Good (PG) signal that
indicates the output voltage is within a specified tolerance of
its target level and no fault condition exists. By default, the PG
pin will assert if the output is within -10%/+15% of the target
voltage. These limits and the polarity of the pin may be
changed via the I 2 C/SMBus interface. See Application Note
AN2033 for details.
A PG delay period is defined as the time from when all
conditions within the ZL6100 for asserting PG are met to
when the PG pin is actually asserted. This feature is
commonly used instead of using an external reset controller
to control external digital logic. By default, the ZL6100 PG
delay is set equal to the soft-start ramp time setting.
Therefore, if the soft-start ramp time is set to 1ms, the PG
delay will be set to 10ms. The PG delay may be set
independently of the soft-start ramp using the I 2 C/SMBus as
described in Application Note AN2033.
Switching Frequency and PLL
The ZL6100 incorporates an internal phase-locked loop
(PLL) to clock the internal circuitry. The PLL can be driven by
an external clock source connected to the SYNC pin. When
using the internal oscillator, the SYNC pin can be configured
as a clock source for other Zilker Labs devices.
15
When the SYNC pin is configured as an output (CFG pin is
tied HIGH), the device will run from its internal oscillator and
will drive the resulting internal oscillator signal (preset to
400kHz) onto the SYNC pin so other devices can be
synchronized to it. The SYNC pin will not be checked for an
incoming clock signal while in this mode.
CONFIGURATION B: SYNC INPUT
When the SYNC pin is configured as an input (CFG pin is
tied LOW), the device will automatically check for a clock
signal on the SYNC pin each time EN is asserted. The
ZL6100’s oscillator will then synchronize with the rising edge
of the external clock.
The incoming clock signal must be in the range of 200kHz to
1.4MHz and must be stable when the enable pin is asserted.
The clock signal must also exhibit the necessary
performance requirements (see the “Electrical
Specifications” table beginning on page 3). In the event of a
loss of the external clock signal, the output voltage may
show transient over/undershoot.
If this happens, the ZL6100 will automatically switch to its
internal oscillator and switch at a frequency close to the
previous incoming frequency.
CONFIGURATION C: SYNC AUTO DETECT
When the SYNC pin is configured in auto detect mode (CFG
pin is left OPEN), the device will automatically check for a
clock signal on the SYNC pin after enable is asserted.
If a clock signal is present, The ZL6100’s oscillator will then
synchronize the rising edge of the external clock. Refer to
If no incoming clock signal is present, the ZL6100 will
configure the switching frequency according to the state of the
SYNC pin as listed in Table 15. In this mode, the ZL6100 will
only read the SYNC pin connection during the start-up
sequence. Changes to SYNC pin connections will not affect
f SW until the power (VDD) is cycled off and on If the user
wishes to run the ZL6100 at a frequency not listed in Table 11,
the switching frequency can be set using an external resistor,
R SYNC , connected between SYNC and SGND using Table 12.
FN6876.3
August 29, 2012
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